EP20K400CF672C7ES - APEX 20KC FPGA, 400K Gates, 672-FBGA | Altera
MPN: EP20K400CF672C7ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $198 | $19,800.00 |
| 250 | $175 | $43,750.00 |
| 500 | $152 | $76,000.00 |
EP20K400CF672C7ES Overview
What is an APEX 20KC FPGA? The APEX 20KC family is a single-chip programmable logic device family that integrates look-up table (LUT)-based logic, embedded system blocks (ESBs) for memory and FIFO, and I/O elements (IOEs) on a unified interconnect architecture (MultiCore architecture). It belongs to the broader hierarchy of Field Programmable Gate Arrays (FPGAs) -> programmable logic devices (PLDs) -> logic ICs -> integrated circuits. APEX 20KC parts are typically used for high-throughput data-path, bus-interface, and glue-logic functions where ASIC-class density is needed without NRE cost.
Key features include 4 phase-locked loops (PLLs) for clock management, MultiVolt I/O supporting 1.5 V, 1.8 V, 2.5 V, and 3.3 V interfaces, JTAG-based IEEE 1149.1 boundary-scan testing, and configuration via passive serial, passive parallel synchronous, passive parallel asynchronous, and JTAG modes. The suffix "C7" indicates a -7 speed grade (commercial), while "ES" denotes an Engineering Sample offering. Per the Altera APEX 20KC datasheet, the device supports hot-socketing and in-system programmability through its dedicated configuration pins.
The device uses a MultiCore interconnect that wires together embedded logic array blocks (LABs), ESBs, and IOEs through row and column FastTrack lines. Each LAB contains 10 logic elements (LEs), and each ESB can be configured as RAM, ROM, or CAM. The combination of high logic density, large embedded memory, and dedicated PLLs makes the APEX 20KC suited for bus-width conversion, video/imaging pipelines, and telecommunications glue logic.
Typical applications include high-speed data-path processing, telecommunications backplane interfaces, video frame buffering, PCI/PCI-X bridging, and DSP co-processing front-ends. The -7 speed grade is suitable for designs where mid-range timing margin is acceptable and cost is prioritized over maximum Fmax.
Designers should verify availability of Engineering Sample (ES) parts against production-grade alternatives, since ES silicon may have parametric differences. For new designs, the Altera Quartus II toolchain supports this device family up through legacy support packages.
This page synthesizes verified distributor pricing, drop-in same-family Altera alternatives drawn from the Site MPN list, and practical configuration/PCB guidance not found in the standalone datasheet.
Drop-in alternatives for EP20K400CF672C7ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400CF672C7ES (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, Speed Grade, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400CF672C7
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP20K400CF672C-7ES
✅ Drop-In✓ In Stock
$132 / Unit
View Datasheet →EP20K400CF672C-7
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400CF672C-8
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP20K400EFC672-2
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K300EFC672-2
✅ Drop-In✓ In Stock
$58.5 / Unit
View Datasheet →EP20K200EFC672-2X
✅ Drop-In✓ In Stock
$128.4 / Unit
View Datasheet →EP20K400CF672C7ES Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Series | EP20K400 |
| Device Type | Loadable PLD / FPGA |
| Logic Elements (Cells) | 16,640 |
| System Gates | 400,000 |
| Embedded Memory (Bits) | 212,992 |
| Total RAM Bits | 212,992 |
| Maximum User I/O | 488 |
| I/O Lines | 484 |
| Input Lines | 488 |
| Number of PLLs | 4 |
| Maximum Internal Clock Frequency | 375.94 MHz |
| Propagation Delay | 1.4 ns |
| Process Technology | 0.18 um CMOS |
| Core Voltage | 1.8 V |
| MultiVolt I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | C7 (commercial, -7) |
| Operating Temperature | 0C to +85C (commercial) |
| Package Type | 672-ball FineLine BGA |
| Package Code | FC-FBGA-B672 |
| Ball Pitch | 1.000 mm |
| Mounting Type | Surface Mount |
EP20K400CF672C7ES fc-fbga-b672 Pin Configuration Guide
Pin configuration for EP20K400CF672C7ES (fc-fbga-b672 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400CF672C7ES.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400CF672C7ES is suitable for 6 applications: Telecommunications Backplane Interface, PCI/PCI-X Bus Bridge, Video Frame Buffer / Imaging Pipeline, DSP Co-Processor Front-End, Industrial Control / Factory Automation, Legacy Telecom Glue Logic Replacement.
Telecommunications Backplane Interface
The EP20K400CF672C7ES's 400,000 system gates and 488 user I/O pins make it a strong fit for telecommunications backplane bridging applications such as TDM-to-packet conversion and high-speed serial fan-out. Its 4 on-chip PLLs allow multiple clock domains to be derived from a single backplane reference, and the 212 Kbits of embedded memory can hold frame buffers and translation tables without external SRAM. The MultiVolt I/O supports 1.5/1.8/2.5/3.3 V signaling, enabling direct interface to legacy 3.3 V line-card ASICs alongside modern 1.5 V devices. Designers should allocate I/O banks carefully and use Quartus II's timing-driven compilation to meet stringent telecom jitter budgets.
Recommended
PCI/PCI-X Bus Bridge
With 16,640 logic elements and 488 I/Os, the EP20K400CF672C7ES can implement a 64-bit PCI-X bus bridge complete with target/initiator state machines, arbiter, and DMA channels. The -7 commercial speed grade supports PCI-X 133 MHz operation with timing closure achievable in Quartus II. The 4 PLLs provide independent clocks for the primary and secondary bus segments, and the embedded ESBs can store scatter-gather descriptor tables on-chip. Engineers should observe PCI-X add-in card impedance specs (65/85 ohm) and place decoupling within 100 mils of every VCCINT/VCCIO pin pair.
Recommended
Video Frame Buffer / Imaging Pipeline
The 212 Kbits of embedded memory distributed across the APEX 20KC's ESBs can be configured as dual-port RAM line buffers supporting real-time video pipelines up to 375 MHz internal clock. Combined with 488 I/O pins, the device can ingest parallel BT.1120 or LVDS camera data and output processed frames to a display controller. The 4 PLLs enable pixel-clock, memory-clock, and output-clock generation from a single reference. Designers should use Quartus II's ALTMEMPHY megafunction for SDR/DDR interface generation and verify line-buffer depth against the worst-case horizontal active pixel count.
Recommended
DSP Co-Processor Front-End
The APEX 20KC's MultiCore architecture supports custom multiply-accumulate datapaths implemented across distributed logic and ESB-based coefficient memory, making the EP20K400CF672C7ES suitable as a DSP co-processor front-end for FIR/IIR filters and FFT pre-processing. The 400K gates accommodate 16-bit parallel datapaths at sample rates approaching 100 MSPS, while the 4 PLLs provide independent clocks for ADC sampling, DSP clocking, and host-interface hand-off. Engineers should pipeline at LE granularity and use Quartus II's DSP megafunctions to leverage hard carry chains for predictable timing.
Recommended
Industrial Control / Factory Automation
With 488 I/O pins, the EP20K400CF672C7ES can fan out to many discrete sensors, encoders, and actuators in factory-automation controllers. The MultiVolt I/O simplifies interfacing with both 24 V-sourced industrial inputs (via external level shifters) and 3.3 V MCUs. The 4 PLLs support multiple motor-control PWM frequencies from a single reference clock. For harsh-environment deployments, the industrial-temp sibling EP20K400EFC672-2 shares the same FBGA-672 footprint but extends the operating range. PCB designs should follow IPC-2221/2222 guidelines and provide adequate thermal relief given the BGA's thermal mass.
Recommended
Legacy Telecom Glue Logic Replacement
The EP20K400CF672C7ES is commonly used to replace discontinued ASICs and bipolar glue logic in legacy telecommunications equipment, where its 400K gates and 488 I/Os can integrate many bus-translation, interrupt-controller, and watchdog functions onto a single chip. Its JTAG-based IEEE 1149.1 boundary-scan support simplifies board-level test for systems originally designed without scan chains. Engineers porting from older PLD families should re-validate timing using Quartus II's TimeQuest timing analyzer and verify that MultiVolt I/O bank assignments match the legacy ASIC's 5 V-tolerant interface requirements via external translation.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400CF672C7ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400CF672C7 | EP20K400CF672C-7ES | EP20K400CF672C-7 | EP20K400CF672C-8 | EP20K400EFC672-2 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-FBGA | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 |
| System Gates | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 | 300,000 (75%) |
| Embedded Memory (bits) | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 | 147,456 (69%) |
| User I/O | 488 | 488 | 488 | 488 | 488 | 488 |
| Number of PLLs | 4 | 4 | 4 | 4 | 4 | 4 |
| Speed Grade | -7 (C7, commercial) | -7 (C7) | -7 ES | -7 | -8 (slower) | -2 industrial |
| Silicon Grade | Engineering Sample (ES) | Production | Engineering Sample | Production | Production | Production industrial |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C (industrial) |
Key Differentiators
- Highest gate density in the 672-FBGA APEX 20KC family (vs EP20K300EFC672-2)
- Faster -7 speed grade option available (vs EP20K400CF672C-8)
- Production-grade variant available for volume migration (vs EP20K400CF672C7)
- Industrial-temp variant available in same package (vs EP20K400EFC672-2)
Design Notes
Estimated: The EP20K400CF672C7ES requires two distinct supply rails - VCCINT (1.8 V core) and VCCIO (1.5/1.8/2.5/3.3 V I/O banks). The 672-FBGA package typically requires 8-12 VCCINT balls and 16-20 VCCIO balls distributed across the package perimeter. Designers should provide at least 4 bulk 100 uF tantalum capacitors near the FBGA plus 0.1 uF and 0.01 uF ceramic decoupling within 100 mils of every VCC/VSS pair to suppress transient current spikes during simultaneous switching output (SSO) events. Use a star-ground topology and isolate analog/digital grounds per the APEX 20KC hardware reference manual.
The 672-ball FineLine BGA with 1.000 mm pitch requires a multi-layer PCB (typically 6-8 layers) with microvia stack-up. Use IPC-2221/2222 design rules and verify BGA fanout with your PCB vendor's design rules before finalizing layout. Recommended stack-up: top signal/GND/power/signal/core/power/GND/signal-bottom with controlled-impedance layers for high-speed I/O. Provide at least one full GND plane directly under the BGA for return-path integrity and thermal dissipation. The BGA's center balls are difficult to probe - include test points on all critical signals at the board periphery.
Differential pairs (LVDS, PCI-X) should be length-matched within 25 mils (about 0.6 mm) and routed with 100 ohm differential impedance. The APEX 20KC supports MultiVolt I/O; group I/O bank assignments by voltage in Quartus II's Pin Planner before finalizing PCB layout to avoid bank re-spins. Decoupling capacitor vias should share the same GND plane via to minimize loop inductance. Leave at least 200 mils of clearance around the BGA for rework accessibility, and consider a heatsink thermal pad pattern for designs with sustained high switching activity.
Engineering Sample (ES) silicon may have parametric differences from production parts and should not be used in volume manufacturing. Always validate ES silicon against the production datasheet before committing to a design. Configuration mode pins (MSEL[3:0]) must be tied to the correct logic levels for the chosen configuration scheme (passive serial, passive parallel, JTAG) - incorrect settings will cause configuration failure. The JTAG TCK pin should be pulled to a defined logic level through a 10 kohm resistor to prevent floating-clock configuration errors. Finally, ensure nCONFIG is held low during power-up until all rails are stable.
Compliance Information
Compliance information was not confirmed in the verified distributor data. APEX 20KC parts pre-date widespread RoHS adoption; Engineering Sample units should be verified for lead-free / RoHS status with the supplier before deployment in RoHS-regulated markets. AEC-Q100 is not applicable since this is a commercial-grade FPGA.
