EP20K400CF672C-8 vs EP20K400CF672C7N Comparison

Detailed side-by-side comparison of EP20K400CF672C-8 by Altera and EP20K400CF672C7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400CF672C-8 EP20K400CF672C7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $95.00 $160.00
Family APEX 20K APEX 20KC
Logic Elements 16,640 β€”
Typical Gates 400,000 400,000
Macros 1,664 β€”
Maximum User I/O 488 488
Number of I/O Banks [DATA_NEEDED: number of I/O banks] β€”
Package Type PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) β€”
Core Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) 1.8 V
I/O Voltage (VCCIO) [DATA_NEEDED: VCCIO options] 3.3 V / 2.5 V banked
Pin-to-Pin Delay (tPD) 1.78 ns (speed grade -8) β€”
Speed Grade -8 β€”
Temperature Grade (C) Commercial, 0 Β°C to 85 Β°C β€”
Process Technology 0.15 Β΅m all-layer copper CMOS 0.18-micron CMOS, all-layer copper interconnect
Embedded Memory Type ESB (RAM / ROM / CAM) β€”
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Passive Parallel β€”
JTAG Support Yes (IEEE 1149.1 boundary-scan) β€”
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status not in provided data]
MSL Level [DATA_NEEDED: MSL level] 3 (per JEDEC J-STD-020)
Maximum System Gates β€” 1,052,000
Logic Elements (LEs) β€” 16,640
Embedded Memory β€” 488 Kbits
User I/O (per catalog) β€” 480 / 502 (per source)
Package β€” 672-ball FineLine BGA (FC-FBGA / BBGA)
Propagation Delay β€” 2.5 ns (catalog) / 1.48 ns (some catalog)
Maximum Frequency β€” 375.94 MHz (internal)
Operating Temperature β€” 0 C to 85 C (Commercial)
Configuration Modes β€” PS, PPS, JTAG

Datasheets & Resources

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