EP20K400CF672C7 vs EP20K400CF672C8AA Comparison
Detailed side-by-side comparison of EP20K400CF672C7 by Altera and EP20K400CF672C8AA by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672C7 | EP20K400CF672C8AA |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $145.00 |
| Series | APEX-20KC | β |
| Family | APEX 20KC (MultiCoreβ’) | APEX 20K |
| Logic Elements / Cells | 16,640 | β |
| System Gates | 400,000 | β |
| Embedded Memory (RAM bits) | 212,992 | β |
| Maximum User I/O | 488 | β |
| Number of I/O Banks | 8 | β |
| Package | 672-BBGA (FC-FBGA, FineLine BGA) | β |
| Pin Count | 672 | β |
| Core Voltage | 1.8 V | β |
| Supply Voltage | 2.5 V (I/O reference) | β |
| Process Technology | 0.15 Β΅m CMOS | β |
| Propagation Delay (tPD) | 2.5 ns | β |
| Maximum Internal Frequency | 375.94 MHz | β |
| Operating Temperature | 0 Β°C to +85 Β°C (Commercial, C-grade) | 0 C to 85 C (Commercial) |
| PLL Count | 4 | β |
| Speed Grade | -7 | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | Non-compliant (legacy product) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Contains lead (legacy BGA finish) | β |
| Number of Logic Elements/Cells | β | 16640 |
| Number of Logic Units (LEs) | β | [DATA_NEEDED: number of LUs] |
| Embedded System Blocks (ESBs) | β | 212 |
| On-chip RAM Bits | β | [DATA_NEEDED: total embedded memory bits] |
| Number of User I/O Pins | β | 488 |
| Package Type | β | 672-ball Fine-Pitch BGA (FBGA) |
| Number of Pins/Balls | β | 672 |
| Supply Voltage (Core) | β | 2.5 V |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, SSTL, HSTL (multi-voltage I/O) |
| Propagation Delay | β | [DATA_NEEDED: typical propagation delay] |
| Packaging | β | Tray |
| Moisture Sensitivity Level (MSL) | β | 3 (168 Hours) |
| Configuration Interface | β | JTAG (IEEE 1149.1), passive serial, passive parallel asynchronous |