EP20K400CF672C7ES vs EP20K400CF672C-8 Comparison
Detailed side-by-side comparison of EP20K400CF672C7ES by Altera and EP20K400CF672C-8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400CF672C7ES
EP20K400CF672C7ES - APEX 20KC FPGA, 400K Gates, 672-FBGA | Altera
EP20K400CF672C7ES ObsoleteAltera
EP20K400CF672C-8
EP20K400CF672C-8 - APEX 20K 400K Gates FPGA, 672-BGA | Altera
EP20K400CF672C-8 ObsoleteSpecification Comparison
| Parameter | EP20K400CF672C7ES | EP20K400CF672C-8 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $152.00 | $95.00 |
| Family | APEX 20KC | APEX 20K |
| Series | EP20K400 | β |
| Device Type | Loadable PLD / FPGA | β |
| Logic Elements (Cells) | 16,640 | β |
| System Gates | 400,000 | β |
| Embedded Memory (Bits) | 212,992 | β |
| Total RAM Bits | 212,992 | β |
| Maximum User I/O | 488 | 488 |
| I/O Lines | 484 | β |
| Input Lines | 488 | β |
| Number of PLLs | 4 | β |
| Maximum Internal Clock Frequency | 375.94 MHz | β |
| Propagation Delay | 1.4 ns | β |
| Process Technology | 0.18 um CMOS | 0.15 Β΅m all-layer copper CMOS |
| Core Voltage | 1.8 V | β |
| MultiVolt I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| Speed Grade | C7 (commercial, -7) | -8 |
| Operating Temperature | 0C to +85C (commercial) | β |
| Package Type | 672-ball FineLine BGA | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Package Code | FC-FBGA-B672 | β |
| Ball Pitch | 1.000 mm | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | β | 16,640 |
| Typical Gates | β | 400,000 |
| Macros | β | 1,664 |
| Number of I/O Banks | β | [DATA_NEEDED: number of I/O banks] |
| Core Voltage (VCCINT) | β | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | β | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | β | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | β | Commercial, 0 Β°C to 85 Β°C |
| Embedded Memory Type | β | ESB (RAM / ROM / CAM) |
| Configuration Interface | β | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | β | Yes (IEEE 1149.1 boundary-scan) |
| MSL Level | β | [DATA_NEEDED: MSL level] |