EP20K400CF672C7ES vs EP20K400CF672C7N Comparison
Detailed side-by-side comparison of EP20K400CF672C7ES by Altera and EP20K400CF672C7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672C7ES | EP20K400CF672C7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $152.00 | $160.00 |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | β |
| Device Type | Loadable PLD / FPGA | β |
| Logic Elements (Cells) | 16,640 | β |
| System Gates | 400,000 | β |
| Embedded Memory (Bits) | 212,992 | β |
| Total RAM Bits | 212,992 | β |
| Maximum User I/O | 488 | 488 |
| I/O Lines | 484 | β |
| Input Lines | 488 | β |
| Number of PLLs | 4 | β |
| Maximum Internal Clock Frequency | 375.94 MHz | β |
| Propagation Delay | 1.4 ns | 2.5 ns (catalog) / 1.48 ns (some catalog) |
| Process Technology | 0.18 um CMOS | 0.18-micron CMOS, all-layer copper interconnect |
| Core Voltage | 1.8 V | β |
| MultiVolt I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| Speed Grade | C7 (commercial, -7) | β |
| Operating Temperature | 0C to +85C (commercial) | 0 C to 85 C (Commercial) |
| Package Type | 672-ball FineLine BGA | β |
| Package Code | FC-FBGA-B672 | β |
| Ball Pitch | 1.000 mm | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status not in provided data] |
| Maximum System Gates | β | 1,052,000 |
| Typical Gates | β | 400,000 |
| Logic Elements (LEs) | β | 16,640 |
| Embedded Memory | β | 488 Kbits |
| User I/O (per catalog) | β | 480 / 502 (per source) |
| Package | β | 672-ball FineLine BGA (FC-FBGA / BBGA) |
| Core Voltage (VCCINT) | β | 1.8 V |
| I/O Voltage (VCCIO) | β | 3.3 V / 2.5 V banked |
| Maximum Frequency | β | 375.94 MHz (internal) |
| MSL Level | β | 3 (per JEDEC J-STD-020) |
| Configuration Modes | β | PS, PPS, JTAG |