EP20K400FC672-3 vs EP20K400FI672-2N Comparison

Detailed side-by-side comparison of EP20K400FC672-3 by Altera and EP20K400FI672-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400FC672-3 EP20K400FI672-2N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $138.00 $188.75
Family APEX 20K APEX 20K
Device Logic Elements 16,640 cells β€”
Typical Gate Count 400,000 system gates β€”
Maximum User I/Os 502 β€”
Propagation Delay 2.5 ns 3.1 ns
Internal Performance 167 MHz β€”
Process Technology 0.22 Β΅m CMOS 0.22 Β΅m CMOS
Core Supply Voltage 2.5 V β€”
Logic Family CMOS, SRAM-based β€”
Package 672-pin FC-FBGA 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA)
Package Code BGA β€”
Number of Terminals 672 β€”
Terminal Form Ball (BGA) β€”
Speed Grade -3 (commercial fastest) -2
Operating Temperature 0 Β°C to 85 Β°C Commercial (0 Β°C to +70 Β°C) [DATA_NEEDED: industrial variant]
Mounting Type Surface Mount Surface Mount
Architecture MultiCore (LUT + Embedded System Blocks) β€”
Programming Method SRAM, JTAG (ByteBlaster) β€”
Lifecycle Status Obsolete / Legacy β€”
RoHS Status [DATA_NEEDED: RoHS status] Compliant (lead-free)
Typical Gates β€” 400,000
Logic Elements / Cells β€” 16,640
Maximum User I/O β€” 488
Embedded Memory Bits β€” 212,992 bits
Embedded Array Blocks (EABs) β€” [DATA_NEEDED: EAB count per family datasheet]
Core Voltage β€” 2.5 V
Maximum Frequency β€” 200 MHz
Package Body Size β€” 27 x 27 mm
Terminal Pitch β€” 1.0 mm
Moisture Sensitivity Level (MSL) β€” 3
Peak Reflow Temperature β€” 220 Β°C
Configuration Modes β€” PS, PPS, PPA, JTAG
Supported I/O Standards β€” LVTTL, LVCMOS, SSTL, HSTL

Datasheets & Resources

Browse All Products Create BOM Request Quote