EP20K400FC672-3 - APEX 20K 400K FPGA, 672-FBGA | Altera
MPN: EP20K400FC672-3 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $198 | $19,800.00 |
| 500 | $162 | $81,000.00 |
| 1,000 | $138 | $138,000.00 |
EP20K400FC672-3 Overview
An FPGA (Field-Programmable Gate Array) is a type of integrated circuit containing an array of programmable logic blocks, interconnect, and I/O cells that an engineer can configure post-manufacture to implement arbitrary digital functions. Within the taxonomy, the APEX 20K belongs to the high-density SRAM-based FPGA family, sitting between CPLDs (Complex Programmable Logic Devices) at lower density and ASICs (Application-Specific Integrated Circuits) at higher NRE cost. APEX 20K pioneered the MultiCore architecture that integrates lookup-table (LUT) logic, embedded system blocks (ESBs) for memory and specialized functions, and high-speed interconnect into a single fabric supporting SOPC integration, where a soft processor core, peripherals, and custom logic coexist on one die.
Key features of the EP20K400FC672-3 include 16,640 logic elements, 502 user I/Os, MultiCore architecture with embedded system blocks, a 672-pin FC-FBGA (Fine-pitch Chip-scale BGA) package for high pin density, 0.22 µm CMOS process technology, 167 MHz internal performance, and a -3 commercial speed grade. The 672-BGA footprint maximizes I/O escape routing for high-bandwidth designs while consuming compact board area compared to equivalent QFP packages.
The APEX 20K architecture combines look-up table logic for combinatorial and registered functions with embedded array blocks (EABs/ESBs) that can be configured as RAM, ROM, or specialized arithmetic pipelines. The MultiCore interconnect is segmented to optimize critical-path delays, supporting 167 MHz operation in pipelined datapaths. Designers targeting the EP20K400FC672-3 typically use the Quartus II or MAX+PLUS II toolchain (legacy support) for synthesis, place-and-route, and timing closure.
Typical applications for the EP20K400FC672-3 span telecommunications infrastructure (ASIC prototyping, glue logic, high-speed datapath bridging), industrial control and factory automation (custom protocol conversion, real-time control), DSP front-ends (preprocessing, filtering), and legacy computing interfaces (PCI bridges, memory controllers). The 502 user I/Os and 16,640-cell density target medium-complexity system integration where ASIC NRE cost is not justifiable.
When designing with this device, verify that the 672-FBGA land pattern and 2.5 V core supply meet your PCB manufacturing and power-delivery budget. Because the APEX 20K family has been in maintenance/legacy status for many years, plan a lifecycle risk-mitigation path: stock a safety inventory, evaluate Cyclone-series successors for new designs, and confirm your compiler toolchain version supports the device. JTAG programming via ByteBlaster or similar download cables is the standard configuration path.
This page synthesizes distributor pricing, drop-in same-package alternatives from the APEX 20K family, and practical design notes not found in the manufacturer datasheet, providing a single decision-grade reference for procurement and engineering teams working with the EP20K400FC672-3.
Drop-in alternatives for EP20K400FC672-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FC672-3 (same form factor and footprint) — differing in Operating Temperature, Package, Speed Grade, Family, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400FC672-2
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFC672-3
✅ Drop-In✓ In Stock
$199.5 / Unit
View Datasheet →EP20K400EFC672-2
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K400CFC672-9
✅ Drop-In✓ In Stock
$325 / Unit
View Datasheet →EP20K400CF672C9
✅ Drop-In✓ In Stock
$390.4 / Unit
View Datasheet →EP20K400CF672C8
✅ Drop-In✓ In Stock
$108 / Unit
View Datasheet →EP20K400FC672-3 Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Device Logic Elements | 16,640 cells |
| Typical Gate Count | 400,000 system gates |
| Maximum User I/Os | 502 |
| Propagation Delay | 2.5 ns |
| Internal Performance | 167 MHz |
| Process Technology | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V |
| Logic Family | CMOS, SRAM-based |
| Package | 672-pin FC-FBGA |
| Package Code | BGA |
| Number of Terminals | 672 |
| Terminal Form | Ball (BGA) |
| Speed Grade | -3 (commercial fastest) |
| Operating Temperature | 0 °C to 85 °C |
| Mounting Type | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) |
| Programming Method | SRAM, JTAG (ByteBlaster) |
| Lifecycle Status | Obsolete / Legacy |
EP20K400FC672-3 bga Pin Configuration Guide
Pin configuration for EP20K400FC672-3 (bga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FC672-3.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FC672-3 is suitable for 7 applications: Telecommunications Infrastructure Gateways, Industrial Control and Factory Automation, ASIC Prototyping and Pre-Silicon Validation, DSP Front-End Preprocessing Pipelines, Legacy Computing Interfaces and Bridges, Medical Imaging Signal Processing, Military and Aerospace Avionics Interfaces.
Telecommunications Infrastructure Gateways
The EP20K400FC672-3's 16,640 logic elements and 502 user I/Os make it well suited for telecommunications gateway designs requiring custom protocol bridging, TDM bus aggregation, and high-density glue logic. Operating from a 2.5 V core, the device supports LVTTL, LVCMOS, and PCI signaling across its I/O banks, enabling direct interface to legacy telecom ASICs without external level translation. The MultiCore architecture with embedded system blocks allows concurrent implementation of UART bridges, HDLC controllers, and ATM segmentation engines on a single fabric, eliminating multi-chip partitioning. The 167 MHz internal Fmax in the -3 grade comfortably supports E1/T1 and 155 Mbps STM-1 framing with margin. For new telecom designs, the APEX 20K family remains a cost-effective legacy platform when Cyclone-series migration is not feasible.
Recommended
Industrial Control and Factory Automation
In industrial control systems, the EP20K400FC672-3 delivers the deterministic logic density required for real-time motor control, PLC scan engines, and fieldbus protocol conversion (Profibus, CANopen, Modbus). The 672-FBGA package provides 502 user I/Os to interface directly with multi-axis encoder inputs, PWM outputs to power stages, and parallel industrial buses without external bus multiplexers. The MultiCore ESBs can be configured as dual-port RAM for inter-task message passing in deterministic control loops. For harsh industrial environments, the EP20K400EFC672-3 variant with industrial temperature range is preferred. Designers benefit from the mature Quartus II toolchain, which provides validated IP cores for common industrial protocols, simplifying IEC 61131-3 style control design and certification.
Recommended
ASIC Prototyping and Pre-Silicon Validation
The EP20K400FC672-3 serves as a robust platform for ASIC prototyping of medium-complexity designs targeting up to 400,000 gate equivalents. Its 16,640 logic cells map cleanly to ASIC gate libraries via the Quartus II synthesis flow, while the 502 user I/Os accommodate ASIC pin counts up to ~400 after de-rating for clock and configuration pins. MultiCore architecture enables realistic timing closure validation of pipelined datapaths up to 167 MHz in the -3 grade, giving high confidence in pre-silicon functional and timing verification. Embedded system blocks can emulate ASIC SRAM macros, reducing the need for companion memory chips on the prototype board. Engineering teams working on telecommunications or storage ASICs commonly leveraged this device for bring-up before committing to mask sets.
Recommended
DSP Front-End Preprocessing Pipelines
The EP20K400FC672-3 fits DSP front-end preprocessing tasks such as digital filtering, FFT pre-processing, and sample-rate conversion for moderate-bandwidth signals. With 167 MHz Fmax and abundant multipliers in the LUT fabric, the device can implement 16-tap FIR filters and 256-point FFT engines running at baseband data rates up to 50 Msps. The 502 I/Os accept wide parallel ADC/DAC buses directly, eliminating intermediate FIFO logic. ESBs configured as RAM provide coefficient storage and overlap-save buffers required by efficient FFT implementations. For new high-performance DSP designs, Stratix or Cyclone V with dedicated DSP blocks are preferred, but for legacy test-and-measurement equipment, the APEX 20K remains a dependable choice.
Recommended
Legacy Computing Interfaces and Bridges
The EP20K400FC672-3 is well matched to legacy computing interface bridging applications, including PCI-to-ISA bridges, VMEbus controllers, and SCSI/ATA protocol converters for industrial computing and military/aerospace retrofits. Its 502 user I/Os comfortably accommodate the wide parallel buses of these legacy interfaces (32-bit PCI requires ~50 signals, VMEbus ~70), while MultiCore ESBs provide the bus-master DMA state machines and FIFOs required for high-throughput bridging. The 2.5 V core and bank-selectable I/O standards (LVTTL, GTL+, PCI) allow direct connection to legacy 3.3 V and 5 V peripherals without external translation. The 167 MHz performance in the -3 grade supports 33 MHz/66 MHz PCI with full timing margin, which is critical for bus-master DMA.
Recommended
Medical Imaging Signal Processing
In medical imaging systems such as ultrasound front-ends and patient monitoring signal chains, the EP20K400FC672-3 provides the logic density required for beamforming, digital filtering, and ECG/EEG feature extraction. The 16,640 logic cells support 64-channel beamforming pipelines for portable ultrasound carts, while the 502 I/Os accept the wide multi-channel ADC buses typical of ultrasound receivers. ESBs configured as dual-port RAM enable per-channel sample storage and circular buffering required for coherent summation. The -3 speed grade delivers 167 MHz Fmax, supporting real-time processing of 40 Msps sample streams. For medical applications, the EP20K400EFC672-3 industrial-temperature variant is recommended to ensure patient-adjacent reliability under varying ambient conditions.
Recommended
Military and Aerospace Avionics Interfaces
The EP20K400FC672-3 supports avionics interface designs including MIL-STD-1553 bridges, ARINC 429 controllers, and discrete signal conditioning for legacy military platforms. The MultiCore architecture allows concurrent implementation of multiple ARINC 429 transmit/receive channels, each requiring a few hundred logic elements plus FIFO storage in ESBs. The 502 user I/Os accommodate the high pin count of avionics backplane connectors, reducing the need for companion bus-expansion chips. While the APEX 20K family lacks formal MIL-PRF-38535 qualification, the EP20K400EFC672-3 industrial-temperature variant is widely used in ruggedized commercial-off-the-shelf (COTS) military designs. New military programs should consider Cyclone or Stratix families with formal QML-V certification for flight-critical applications.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FC672-3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400FC672-2 | EP20K400EFC672-3 | EP20K400EFC672-2 | EP20K400CFC672-9 | EP20K400CF672C9 |
|---|---|---|---|---|---|---|
| Package | 672-pin FC-FBGA | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) | 672-pin FC-FBGA (same) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Logic Elements | 16,640 cells | 16,640 cells (same) | 16,640 cells (same) | 16,640 cells (same) | 16,640 cells (same) | 16,640 cells (same) |
| User I/Os | 502 | 502 (same) | 502 (same) | 502 (same) | 502 (same) | 502 (same) |
| Speed Grade | -3 (fastest commercial) | -2 (~10-15% slower) | -3 (same) | -2 (~10-15% slower) | -9 (~30% slower) | C9 (~20-25% slower) |
| Temperature Grade | Commercial (0 to 85 °C) | Commercial | Industrial | Industrial | Commercial | Commercial |
| Core Voltage | 2.5 V | 2.5 V (same) | 2.5 V (same) | 2.5 V (same) | 2.5 V (same) | 2.5 V (same) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest commercial speed grade in the APEX 20K family (vs EP20K400FC672-2)
- Industrial temperature range option in same package (vs EP20K400EFC672-3)
- Highest I/O count density for the family at 672 pins (vs EP20K400EBC652-3)
Design Notes
Estimated: At 167 MHz internal operation with 80% logic utilization, the EP20K400FC672-3 core power dissipation is approximately 1.5–2.5 W (datasheet figure for APEX 20K typical). The 672-FBGA package has θJA around 18 °C/W with adequate PCB thermal vias. For commercial-temperature applications, provide at least 4 thermal vias in a 4x4 grid under the central die region and avoid blocking airflow above the package. For industrial-temperature variants like EP20K400EFC672-3, derate ambient temperature by 10 °C to maintain timing margin over the -40 °C to 100 °C range.
The 672-FBGA package uses a 1.0 mm ball pitch, which mandates microvia or via-in-pad PCB technology. According to APEX 20K layout guidelines, escape routing on the top layer requires 4-mil trace/space rules; signal layers must be paired with continuous reference planes to maintain 50 Ω controlled impedance for LVTTL and LVCMOS interfaces. Decoupling requires at least 20 low-ESL ceramic capacitors (0.1 µF and 0.01 µF in parallel) within 5 mm of the package, plus a bulk 100 µF tantalum or polymer capacitor on the 2.5 V rail. JTAG chain routing must be kept short and away from high-speed clock traces.
Do not confuse the APEX 20K (SRAM-based) with the MAX 7000/3000 (EEPROM-based) CPLD families - configuration methods differ and JTAG programming files are not interchangeable. According to Altera application notes, the EP20K400FC672-3 requires SRAM configuration on every power-up, so a configuration PROM (EPC16 or compatible) must be present on the board, or JTAG boot must be reliable in production. Designers often overlook that the APEX 20K I/O banks have specific VCCIO requirements; mixing 3.3 V and 5 V inputs on the same bank will damage the device. Always consult the pinout table before PCB layout to assign bank voltages correctly.
Differential pairs (LVDS, though APEX 20K has limited LVDS support - primarily LVTTL/LVCMOS) must be length-matched within 150 mil. Clock traces should be series-terminated at the source with a 33 Ω resistor to dampen reflections. According to APEX 20K reference designs, dedicated PLL input pins (CLK0-CLK3) must be used for global clocks; routing clocks through general-purpose I/O causes excessive skew. ESB dual-port RAM blocks should be floorplanned close to the datapath that accesses them to minimize routing congestion in the Quartus II fitter.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status not explicitly stated in the verified web data for the EP20K400FC672-3. APEX 20K family predates widespread RoHS transition; some date codes may be non-compliant. Verify with the distributor's lot-specific documentation before procurement for RoHS-restricted applications.
