EP20K400FI672-2N vs EP20K400FC672-3 Comparison

Detailed side-by-side comparison of EP20K400FI672-2N by Altera and EP20K400FC672-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400FI672-2N EP20K400FC672-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $188.75 $138.00
Family APEX 20K APEX 20K
Typical Gates 400,000 β€”
Logic Elements / Cells 16,640 β€”
Maximum User I/O 488 β€”
Embedded Memory Bits 212,992 bits β€”
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count per family datasheet] β€”
Process Technology 0.22 Β΅m CMOS 0.22 Β΅m CMOS
Core Voltage 2.5 V β€”
Maximum Frequency 200 MHz β€”
Package 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) 672-pin FC-FBGA
Package Body Size 27 x 27 mm β€”
Terminal Pitch 1.0 mm β€”
Propagation Delay 3.1 ns 2.5 ns
Speed Grade -2 -3 (commercial fastest)
Operating Temperature Commercial (0 Β°C to +70 Β°C) [DATA_NEEDED: industrial variant] 0 Β°C to 85 Β°C
Moisture Sensitivity Level (MSL) 3 β€”
Peak Reflow Temperature 220 Β°C β€”
Mounting Type Surface Mount Surface Mount
RoHS Status Compliant (lead-free) [DATA_NEEDED: RoHS status]
Configuration Modes PS, PPS, PPA, JTAG β€”
Supported I/O Standards LVTTL, LVCMOS, SSTL, HSTL β€”
Device Logic Elements β€” 16,640 cells
Typical Gate Count β€” 400,000 system gates
Maximum User I/Os β€” 502
Internal Performance β€” 167 MHz
Core Supply Voltage β€” 2.5 V
Logic Family β€” CMOS, SRAM-based
Package Code β€” BGA
Number of Terminals β€” 672
Terminal Form β€” Ball (BGA)
Architecture β€” MultiCore (LUT + Embedded System Blocks)
Programming Method β€” SRAM, JTAG (ByteBlaster)
Lifecycle Status β€” Obsolete / Legacy

Datasheets & Resources

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