EP20K400GC655-2V vs EP20K400GC655-1 Comparison
Detailed side-by-side comparison of EP20K400GC655-2V by Altera and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V β Last Time BuyIntel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-2V | EP20K400GC655-1 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.75 | $135.00 |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20K |
| Logic Elements | 16,640 | 16,640 |
| Total RAM Bits | 212,992 | 212,992 |
| System Gates | ~400,000 (typical marketing figure) | β |
| Number of I/O | [DATA_NEEDED: I/O count] | β |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | β |
| Propagation Delay | 3.000 ns | 2.5 ns |
| Process Technology | CMOS, 0.18 um | 0.22 Β΅m CMOS |
| LVDS Support | Yes | β |
| Package | 655-CPGA (62.48 x 62.48 mm) | 655-pin CPGA (Ceramic Pin Grid Array) |
| Package Type | Ceramic Pin Grid Array, through-hole | β |
| Mounting Type | Through-hole (CPGA) | Through-Hole |
| Speed Grade | -2 | β |
| Operating Temperature | [DATA_NEEDED: temperature grade] | 0 Β°C to +85 Β°C (commercial) |
| RoHS Status | unknown | Non-compliant (contains lead in ceramic package) |
| Lead-Free | unknown | β |
| Architecture | MultiCore (LUT + product-term + embedded memory) | β |
| Maximum Gates | β | 1,052,000 |
| Typical Gates | β | 400,000 |
| Embedded System Blocks (ESBs) | β | 4 |
| Maximum User I/O | β | 502 |
| Dedicated Inputs | β | 6 |
| Core Supply Voltage | β | 2.5 V |
| I/O Supply Voltage | β | 3.3 V |
| Maximum Internal Frequency | β | 250 MHz |
| Pin Count | β | 655 |
| Configuration Modes | β | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |