EP20K400GI655-1V vs EP20K400GC655-3V Comparison
Detailed side-by-side comparison of EP20K400GI655-1V by Intel and EP20K400GC655-3V by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel
EP20K400GI655-1V β Last Time Buy
Specification Comparison
| Parameter | EP20K400GI655-1V | EP20K400GC655-3V |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $155.00 | $160.00 |
| Family | APEX 20K | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) |
| Typical Gates | 400,000 | β |
| Logic Elements | 16,640 | 16640 |
| Maximum User I/O | 502 | β |
| Dedicated Inputs | 4 | β |
| Package Type | CBGA-655 (Ceramic Ball Grid Array) | β |
| Package Code (JESD-30) | S-CPGA-P655 | β |
| Package Equivalence Code | SPGA655, 47x47 | SPGA655, 47x47 |
| Process Technology | CMOS | CMOS |
| Propagation Delay | 2.5 ns | 3.6 ns |
| Core Supply Voltage | 2.5 V | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Supply Voltage | 2.5 V / 3.3 V | β |
| Configuration | In-system programmable via JTAG | SRAM-based (requires EPC configuration device) |
| Boundary Scan | IEEE 1149.1 JTAG | β |
| Operating Temperature | [DATA_NEEDED: industrial vs military grade] | [DATA_NEEDED: commercial / industrial / military grade] |
| MSL Level | 1 | β |
| Package Body Material | Ceramic | β |
| RoHS Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] |
| Series | β | APEX-20KC |
| Manufacturer | β | Altera (now Intel) |
| Total RAM Bits | β | 212992 |
| Typical Gate Count | β | 400000 |
| Number of User I/O | β | 496 |
| Maximum Clock Frequency | β | 714.2 MHz |
| Speed Grade | β | -3V (commercial temperature, Vcc 1.8 V) |
| Package | β | 655-BCPGA (62.48 mm x 62.48 mm) |
| Mounting Type | β | Through Hole (CPGA) |
| Peak Reflow Temperature | β | 220 C |
| JTAG Support | β | Yes (IEEE 1149.1 boundary-scan) |