EP20K400GC655-3V - APEX 20KC FPGA 400K Gates 655-CPGA | Intel
MPN: EP20K400GC655-3V ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $250 | $250.00 |
| 10 | $220 | $2,200.00 |
| 100 | $195 | $19,500.00 |
| 500 | $175 | $87,500.00 |
| 1,000 | $160 | $160,000.00 |
EP20K400GC655-3V Overview
A Field Programmable Gate Array (FPGA) is a programmable logic device (PLD) that allows designers to configure digital logic, memory blocks, and I/O via SRAM-based configuration cells. The APEX 20KC series is a programmable logic device family positioned between traditional CPLDs and high-end FPGAs - it is a PLD in the broader semiconductor taxonomy: PLD -> FPGA -> high-density SRAM-based FPGA -> APEX 20KC family. This device family targets system-on-a-programmable-chip integration with on-chip memory and DSP capability.
Key features of the EP20K400GC655-3V include 400,000 typical gate count, 496 user I/O pins, embedded array blocks (EABs) for memory implementation, LVDS I/O support, JTAG boundary-scan testing, and a peak reflow temperature of 220 C. The 1.8 V core supply (1.71 V to 1.89 V tolerance) reduces power consumption compared with the older 2.5 V APEX 20K devices. The speed grade -3V indicates a commercial temperature range variant.
From an architectural standpoint, the APEX 20KC device combines LUT-based logic for register-intensive functions with product-term logic for fast arithmetic paths, allowing designers to map glue logic and datapath blocks into a single device. The embedded system blocks (ESBs) provide true dual-port RAM, ROM, and FIFO functions. Configuration is SRAM-based, requiring a configuration device such as an EPC configuration PROM for stand-alone operation.
Typical applications for the EP20K400GC655-3V include telecommunications infrastructure (ATM switching, SONET framer interfaces), high-speed datapath glue logic, DSP co-processing, industrial control and test equipment, and legacy ASIC prototyping. The high pin count (496 user I/O) makes it suitable for bus-intensive designs such as processor peripherals, memory interfaces, and parallel data acquisition systems. The CPGA package is also well suited to prototyping and military/aerospace-grade designs requiring hermetic packaging.
When designing with this device, pay close attention to power sequencing of the 1.8 V core and I/O banks because the SRAM configuration cells require proper power-up sequencing to avoid latch-up. Use the Quartus II or MAX+PLUS II toolchain for synthesis and place-and-route. The 655-pin CPGA footprint requires a through-hole PCB land pattern with adequate via-in-pad or via-farm stitching for signal integrity at high toggle rates.
This page synthesizes distributor pricing, APEX 20KC family drop-in alternatives from the Site MPN list, and practical design notes that go beyond the manufacturer datasheet's typical application section.
Drop-in alternatives for EP20K400GC655-3V — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400GC655-3V (same form factor and footprint) — differing in Process Technology, Family, Mounting Type, Speed Grade, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400GC655-3
✅ Drop-In✓ In Stock
$310 / Unit
View Datasheet →EP20K400GC655-2V
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K400GC655-2
✅ Drop-In✓ In Stock
$80 / Unit
View Datasheet →EP20K400GC655-1V
✅ Drop-In✓ In Stock
$555 / Unit
View Datasheet →EP20K400GC655-2X
✅ Drop-In✓ In Stock
$175 / Unit
View Datasheet →EP20K400GC655-1X
✅ Drop-In✓ In Stock
$193.04 / Unit
View Datasheet →EP20K400GC655-3V Maximum Ratings & Electrical Characteristics
| Series | APEX-20KC |
| Family | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) |
| Manufacturer | Altera (now Intel) |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) |
| Logic Elements | 16640 |
| Total RAM Bits | 212992 |
| Typical Gate Count | 400000 |
| Number of User I/O | 496 |
| Maximum Clock Frequency | 714.2 MHz |
| Propagation Delay | 3.6 ns |
| Speed Grade | -3V (commercial temperature, Vcc 1.8 V) |
| Package | 655-BCPGA (62.48 mm x 62.48 mm) |
| Package Equivalence Code | SPGA655, 47x47 |
| Mounting Type | Through Hole (CPGA) |
| Peak Reflow Temperature | 220 C |
| Process Technology | CMOS |
| Configuration | SRAM-based (requires EPC configuration device) |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) |
EP20K400GC655-3V Pin Configuration
| Pin A1 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A2 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A3 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A4 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A5 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A6 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A7 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A8 | GND — Ground (digital) |
| Pin A9 | I/O — General-purpose user I/O pin (bank 1) |
| Pin A10 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B1 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B2 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B3 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B4 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B5 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B6 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B7 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B8 | VCCINT — Core supply voltage (1.71 V to 1.89 V) |
| Pin B9 | I/O — General-purpose user I/O pin (bank 1) |
| Pin B10 | I/O — General-purpose user I/O pin (bank 1) |
| Pin C1 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C2 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C3 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C4 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C5 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C6 | VCCIO — I/O supply voltage (bank 2) |
| Pin C7 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C8 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C9 | I/O — General-purpose user I/O pin (bank 2) |
| Pin C10 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D1 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D2 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D3 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D4 | GND — Ground (digital) |
| Pin D5 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D6 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D7 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D8 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D9 | I/O — General-purpose user I/O pin (bank 2) |
| Pin D10 | I/O — General-purpose user I/O pin (bank 2) |
Typical Applications
EP20K400GC655-3V is suitable for 6 applications: Telecommunications Infrastructure, Legacy ASIC Prototyping, Industrial Control and Test Equipment, Military and Aerospace Systems, High-Speed Datapath Glue Logic, DSP Co-Processing.
Telecommunications Infrastructure
The EP20K400GC655-3V fits telecom infrastructure applications such as ATM switching fabrics and SONET/SDH framer interfaces because its 16,640 logic elements and 212,992 bits of embedded RAM provide the parallel datapath capacity required for high-speed cell/packet processing. Its 714.2 MHz maximum clock frequency supports the line-rate processing of OC-48/STM-16 class systems, and the 496 user I/Os accommodate wide parallel bus connections to framers, mappers, and PHY devices. The 655-pin BCPGA package's hermetic ceramic construction also suits the long-life, reliability-focused requirements of carrier-grade telecom hardware. Performance consideration: LVDS I/O support enables low-EMI differential signaling for backplane interfaces, but designers must follow Altera's LVDS termination and PCB-layout guidelines to avoid signal-integrity issues.
Recommended
Legacy ASIC Prototyping
The EP20K400GC655-3V is well suited for prototyping legacy ASIC designs because its 400,000 typical gate capacity accommodates most mid-complexity ASIC replacements, and its APEX 20KC MultiCore architecture (LUT + product-term logic + ESBs) lets designers map both datapath and control logic into a single device. The SRAM-based configuration allows unlimited design iterations without package replacement - a critical benefit during ASIC emulation. The 655-pin BCPGA through-hole package simplifies hand-rework and socketed testing on prototype boards. Trade-off: SRAM configuration means the design must be reloaded on every power-up via a configuration PROM or JTAG, so production deployment requires an EPC configuration device.
Recommended
Industrial Control and Test Equipment
The EP20K400GC655-3V suits industrial control and test equipment where its 16,640 logic elements, embedded system blocks, and 496 user I/Os enable integration of control logic, data acquisition, and parallel bus interfaces in a single chip. The LVDS I/O support reduces EMI in factory-floor environments, and the 1.8 V core lowers power consumption for thermally constrained industrial enclosures. The APEX 20KC device can also implement DSP functions (filters, FFTs) in the ESB-based multiplier blocks. Performance trade-off: at 1.8 V core, the device must be paired with 1.8 V regulators (not legacy 2.5 V APEX 20K designs), and the through-hole BCPGA requires sockets or wave soldering on the production line.
Recommended
Military and Aerospace Systems
The EP20K400GC655-3V is appropriate for military and aerospace applications because the 655-pin ceramic pin grid array (CPGA/BCPGA) package provides hermetic sealing for harsh-environment and high-reliability deployments, including avionics, missile guidance, and satellite subsystems. The SRAM-based fabric is radiation-tolerant to commercial space levels when paired with periodic scrubbing, and the 16,640 logic elements support complex state-machine and signal-processing tasks. The 1.8 V core supply reduces in-rush current during spacecraft power-up. Trade-off: the BCPGA through-hole footprint increases PCB area and weight vs BGA packages - aerospace designers must trade off hermeticity vs mass/volume.
Recommended
High-Speed Datapath Glue Logic
The EP20K400GC655-3V acts as high-speed glue logic between processors, memory controllers, and peripherals in complex board designs, because the 16,640 logic elements and 714.2 MHz maximum clock frequency can absorb bus-bridge, FIFO, and protocol-conversion functions that would otherwise require several discrete CPLDs. The 212,992 bits of embedded RAM are sufficient for moderate-size buffer FIFOs in streaming data applications. The 496 user I/Os accommodate wide memory buses and parallel peripheral interfaces. Performance trade-off: the 655-BCPGA package limits the device to through-hole assembly; for high-density SMT production, designers should select the 672-BGA variant EP20K400FI672-3V instead.
Recommended
DSP Co-Processing
The EP20K400GC655-3V serves as a DSP co-processor for fixed-point filter, FFT, and convolution operations in image-processing, audio-processing, and baseband signal-processing systems. The APEX 20KC architecture's embedded system blocks (ESBs) support multiplier implementations, and 212,992 RAM bits provide coefficient and data buffer storage. The 1.8 V core keeps co-processor power consumption manageable in embedded and battery-powered systems. Trade-off: modern designs targeting higher DSP throughput should evaluate Cyclone or Stratix families instead, because APEX 20KC lacks dedicated DSP blocks and is limited to roughly 100 MHz DSP clock rates.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400GC655-3V — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400GC655-3 | EP20K400GC655-2V | EP20K400GC655-2 | EP20K400GC655-1V |
|---|---|---|---|---|---|
| Package | 655-BCPGA (62.48x62.48 mm) | 655-BCPGA - same | 655-BCPGA - same | 655-BCPGA - same | 655-BCPGA - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 16640 | 16640 | 16640 | 16640 | 16640 |
| Total RAM Bits | 212992 | 212992 | 212992 | 212992 | 212992 |
| User I/O | 496 | 496 | 496 | 496 | 496 |
| Core Voltage | 1.8 V (1.71-1.89 V) | 2.5 V (no-V variant) | 1.8 V | 2.5 V | 1.8 V |
| Speed Grade | -3V (fastest of -V family) | -3 (fastest overall, 2.5 V core) | -2V (mid-grade 1.8 V) | -2 (mid-grade 2.5 V) | -1V (slowest 1.8 V grade) |
| Process / Family | CMOS, APEX 20KC | CMOS, APEX 20K (2.5 V) | CMOS, APEX 20KC | CMOS, APEX 20K (2.5 V) | CMOS, APEX 20KC |
Key Differentiators
- Hermetic 655-pin BCPGA package for high-reliability applications (vs EP20K400FI672-3V (672-pin BGA))
- 1.8 V APEX 20KC core for lower power than 2.5 V APEX 20K (vs EP20K400GC655-3 (2.5 V APEX 20K))
- Highest speed grade of the -V (1.8 V) family (vs EP20K400GC655-2V)
Design Notes
The EP20K400GC655-3V requires a clean 1.8 V core supply within the 1.71 V to 1.89 V tolerance window. Estimated: at 50% toggle rate across 16640 logic elements, the core current draw can reach 1.5-2.5 A transient peaks. Use a low-ESR decoupling network of 100 uF bulk + 10 x 0.1 uF + 4 x 1 nF ceramic capacitors distributed around the BCPGA pin grid. Power-up sequencing must follow the Altera APEX 20KC handbook - VCCINT (1.8 V core) and VCCIO (per bank) must ramp monotonically to avoid latch-up of the SRAM configuration cells.
The 655-pin BCPGA requires a through-hole PCB land pattern with 1.0 mm to 1.2 mm plated through-holes on a 2.54 mm grid (47x47 array). Add at least 6 thermal vias under the ceramic package center for heat dissipation; the BCPGA has a theta_JA in the 8-12 C/W range (per Altera packaging notes). Use a socket (e.g., 3M Textool or Yamaichi) during prototype bring-up to allow rework; for production, hand-solder or use selective soldering because the BCPGA is not compatible with standard SMT reflow. Ground and VCCINT pins should be tied to internal power planes with short, low-inductance vias.
Do not confuse the EP20K400GC655-3V (1.8 V APEX 20KC, suffix V) with the EP20K400GC655-3 (2.5 V APEX 20K, no-V suffix). They share the same 655-BCPGA pinout and same die architecture, but applying 2.5 V to the -3V variant will damage the device because the core transistors are scaled for 1.8 V operation. Verify the datasheet's VCCINT range (1.71 V to 1.89 V for -V) before PCB power-up. Also note that SRAM-based configuration is volatile: without a connected EPC configuration PROM or JTAG programmer, the device will not function after power-up.
For LVDS I/O operation, follow Altera's APEX 20KC LVDS reference design guidelines: matched differential pair lengths within 50 mils, 100-ohm differential impedance, AC-coupling capacitors near the receiver side, and 100-ohm termination resistor at the receiver. The BCPGA's long lead inductance (~2-3 nH per pin) requires careful via stitching and ground-return planning for signals above 200 MHz. Consider using the slower -2V or -1V speed grade if signal-integrity margins are tight, because the slower slew rate reduces simultaneous-switching noise (SSN) on the parallel I/O banks.
Compliance Information
The 655-BCPGA ceramic package is typically non-RoHS because of lead-based ceramic seals common in hermetic packages; this should be verified against the manufacturer's declaration. The part is obsolete/EOL; compliance status beyond RoHS basic declaration is generally not maintained for EOL parts. AEC-Q100 is not applicable because the part is not marketed for automotive use.
