EP20K600CB652C-8 vs EP20K600CB652C7ES Comparison

Detailed side-by-side comparison of EP20K600CB652C-8 by Altera and EP20K600CB652C7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C-8 EP20K600CB652C7ES
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $86.00 $195.00
Series APEX 20KC β€”
Family APEX 20KC (MultiCore) APEX 20KC
Typical Gates 600,000 β€”
Logic Elements 24,320 24,320
Embedded RAM 311,296 bits β€”
User I/Os 488 β€”
Propagation Delay 1.48 ns (per published source) 1.6 ns
Package 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch) β€”
Mounting Type Surface Mount (thermally enhanced) Surface Mount (BGA)
Operating Temperature 0 C to 85 C (commercial) 0 Β°C to +85 Β°C (commercial)
Speed Grade -8 (slowest, most timing margin) β€”
VCCIO Options 1.8 V / 2.5 V / 3.3 V β€”
Process 0.15 Β΅m all-layer copper metal β€”
PCI Compliance PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit β€”
Memory Interface Support DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS β€”
Configuration Enhanced (EPC) bitstream β€”
System Gates β€” 600,000
Maximum System Gates β€” 1,053,840
Embedded Memory Bits β€” 311,296
Embedded System Blocks (ESB) β€” 26
Maximum User I/O β€” 488
User I/O (this package) β€” 488 (652-BGA)
Supply Voltage - Core β€” 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency β€” 1666.6 MHz
Process Technology β€” 0.15 Β΅m CMOS
Package Type β€” 652-ball FineLine BGA
JEDEC Package Code β€” S-PBGA-B652
Configuration Modes β€” Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan β€” IEEE 1149.1 compliant
RoHS Status β€” [DATA_NEEDED: RoHS status]
PLLs β€” 4

Datasheets & Resources

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