EP20K600CB652C7 vs EP20K600CB652C7ES Comparison

Detailed side-by-side comparison of EP20K600CB652C7 by Altera and EP20K600CB652C7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C7 EP20K600CB652C7ES
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $1,320.00 $195.00
Series APEX 20K β€”
Family APEX 20KC APEX 20KC
System Gates 600,000 600,000
Logic Elements 24,320 24,320
Embedded RAM 311,296 bits β€”
User I/O Count 488 β€”
Package 652-ball BGA β€”
Process Technology 0.15 Β΅m CMOS (all-layer copper interconnect) 0.15 Β΅m CMOS
Core Voltage 1.8 V β€”
I/O Voltage Support 1.8V / 2.5V / 3.3V / 5V (MultiVolt) β€”
Maximum Frequency 375.94 MHz β€”
Architecture MultiCore (LUT + embedded memory) β€”
Operating Temperature Commercial (0C to +70C) 0 Β°C to +85 Β°C (commercial)
Speed Grade C7 β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Maximum System Gates β€” 1,053,840
Embedded Memory Bits β€” 311,296
Embedded System Blocks (ESB) β€” 26
Maximum User I/O β€” 488
User I/O (this package) β€” 488 (652-BGA)
Supply Voltage - Core β€” 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency β€” 1666.6 MHz
Propagation Delay β€” 1.6 ns
Package Type β€” 652-ball FineLine BGA
JEDEC Package Code β€” S-PBGA-B652
Configuration Modes β€” Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan β€” IEEE 1149.1 compliant
PLLs β€” 4
Mounting Type β€” Surface Mount (BGA)

Datasheets & Resources

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