EP20K600CB652C7ES vs EP20K600CB652C-8 Comparison

Detailed side-by-side comparison of EP20K600CB652C7ES by Altera and EP20K600CB652C-8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C7ES EP20K600CB652C-8
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $195.00 $86.00
Family APEX 20KC APEX 20KC (MultiCore)
Logic Elements 24,320 24,320
System Gates 600,000 β€”
Maximum System Gates 1,053,840 β€”
Embedded Memory Bits 311,296 β€”
Embedded System Blocks (ESB) 26 β€”
Maximum User I/O 488 β€”
User I/O (this package) 488 (652-BGA) β€”
Supply Voltage - Core 1.71 V to 1.89 V (1.8 V nominal) β€”
Maximum Internal Clock Frequency 1666.6 MHz β€”
Propagation Delay 1.6 ns 1.48 ns (per published source)
Process Technology 0.15 Β΅m CMOS β€”
Operating Temperature 0 Β°C to +85 Β°C (commercial) 0 C to 85 C (commercial)
Package Type 652-ball FineLine BGA β€”
JEDEC Package Code S-PBGA-B652 β€”
Configuration Modes Passive Serial, Passive Parallel, JTAG β€”
JTAG Boundary Scan IEEE 1149.1 compliant β€”
RoHS Status [DATA_NEEDED: RoHS status] β€”
PLLs 4 β€”
Mounting Type Surface Mount (BGA) Surface Mount (thermally enhanced)
Series β€” APEX 20KC
Typical Gates β€” 600,000
Embedded RAM β€” 311,296 bits
User I/Os β€” 488
Package β€” 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch)
Speed Grade β€” -8 (slowest, most timing margin)
VCCIO Options β€” 1.8 V / 2.5 V / 3.3 V
Process β€” 0.15 Β΅m all-layer copper metal
PCI Compliance β€” PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit
Memory Interface Support β€” DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS
Configuration β€” Enhanced (EPC) bitstream

Datasheets & Resources

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