EP20K600CB652C7ES vs EP20K600CB652C7 Comparison
Detailed side-by-side comparison of EP20K600CB652C7ES by Altera and EP20K600CB652C7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CB652C7ES | EP20K600CB652C7 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $1,320.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 |
| System Gates | 600,000 | 600,000 |
| Maximum System Gates | 1,053,840 | β |
| Embedded Memory Bits | 311,296 | β |
| Embedded System Blocks (ESB) | 26 | β |
| Maximum User I/O | 488 | β |
| User I/O (this package) | 488 (652-BGA) | β |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | β |
| Maximum Internal Clock Frequency | 1666.6 MHz | β |
| Propagation Delay | 1.6 ns | β |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m CMOS (all-layer copper interconnect) |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) | Commercial (0C to +70C) |
| Package Type | 652-ball FineLine BGA | β |
| JEDEC Package Code | S-PBGA-B652 | β |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | β |
| JTAG Boundary Scan | IEEE 1149.1 compliant | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| PLLs | 4 | β |
| Mounting Type | Surface Mount (BGA) | β |
| Series | β | APEX 20K |
| Embedded RAM | β | 311,296 bits |
| User I/O Count | β | 488 |
| Package | β | 652-ball BGA |
| Core Voltage | β | 1.8 V |
| I/O Voltage Support | β | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Maximum Frequency | β | 375.94 MHz |
| Architecture | β | MultiCore (LUT + embedded memory) |
| Speed Grade | β | C7 |