EP20K600CF672C-8 vs EP20K400CF672C-8 Comparison

Detailed side-by-side comparison of EP20K600CF672C-8 by Altera and EP20K400CF672C-8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672C-8 EP20K400CF672C-8
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $1,150.00 $95.00
Series APEX 20KC β€”
Device Type FPGA (Field Programmable Gate Array) β€”
Typical Gates 600,000 400,000
Logic Elements (LEs) 24,320 β€”
Embedded Memory Bits 311,296 β€”
Maximum User I/Os 508 β€”
Number of Pins 672 β€”
Package Type 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch)
Speed Grade -8 -8
Propagation Delay (tPD) 1.48 ns β€”
Process Technology 0.15 micrometer all-layer copper-metal 0.15 Β΅m all-layer copper CMOS
Architecture MultiCore (LUT logic + embedded memory) β€”
Operating Temperature Range 0C to +85C (commercial) β€”
Supply Voltage Multi-rail (core + I/O banks) β€”
Configuration Method Serial / parallel / JTAG β€”
Pin Compatibility Pin-compatible with APEX 20KE family β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Family β€” APEX 20K
Logic Elements β€” 16,640
Macros β€” 1,664
Maximum User I/O β€” 488
Number of I/O Banks β€” [DATA_NEEDED: number of I/O banks]
Core Voltage (VCCINT) β€” 1.8 V nominal (1.71 V to 1.89 V)
I/O Voltage (VCCIO) β€” [DATA_NEEDED: VCCIO options]
Pin-to-Pin Delay (tPD) β€” 1.78 ns (speed grade -8)
Temperature Grade (C) β€” Commercial, 0 Β°C to 85 Β°C
Embedded Memory Type β€” ESB (RAM / ROM / CAM)
Configuration Interface β€” JTAG (IEEE 1149.1), Passive Serial, Passive Parallel
JTAG Support β€” Yes (IEEE 1149.1 boundary-scan)
Mounting Type β€” Surface Mount (BGA)
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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