EP20K600CF672C-8 - APEX 20KC FPGA 600K Gates 24320 LEs 672-BGA | Intel / Altera
MPN: EP20K600CF672C-8 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1531.94 | $1,531.94 |
| 10 | $1438.5 | $14,385.00 |
| 100 | $1320.1 | $132,010.00 |
| 500 | $1225.55 | $612,775.00 |
| 1,000 | $1150 | $1,150,000.00 |
EP20K600CF672C-8 Overview
An FPGA (Field Programmable Gate Array) is a programmable logic device that combines configurable logic blocks, embedded memory, and routing interconnects into a single semiconductor. FPGAs belong to the broader family of programmable logic devices (PLDs) and sit alongside CPLDs as the highest-density programmable option. They are widely used for high-speed digital signal processing, communications interfaces, glue logic, prototyping of ASICs, and parallel compute acceleration, offering hardware-reconfigurable parallelism that microcontrollers cannot match.
Key features of the EP20K600CF672C-8 include the MultiCore architecture that integrates lookup-table (LUT) logic with embedded memory blocks (ESBs) optimized for FIFO and dual-port RAM, a high-performance low-power copper interconnect, built-in PCI-compliant I/O, and support for multiple I/O standards including LVTTL, LVCMOS, PCI, GTL+, SSTL-2, SSTL-3, LVDS, and LVPECL. The -8 speed grade targets designs where register-rich pipelined architectures can hide combinational latency.
From an architectural standpoint the device combines four-input LUT-based logic elements with embedded memory, distributed RAM, and dedicated carry chains, making it suitable for both register-intensive datapaths and memory-mapped peripherals. The 672-pin FineLine BGA package exposes 508 user I/Os, providing generous board-level connectivity for parallel buses, memory interfaces, and high-speed serial channels.
Typical applications include telecom backplane glue logic, PCI bus bridges and controllers, high-speed datapath designs in test and measurement, video processing pipelines, network switch fabric adaptation, and ASIC prototyping for communications ASICs. The wide I/O count also makes it attractive for legacy parallel-bus replacement designs.
When designing with this part, engineers should pay close attention to power sequencing, JTAG configuration, and I/O bank voltage grouping, because the APEX 20KC architecture predates modern power-management features and requires careful PCB layout to meet signal-integrity targets at the -8 speed grade.
This page consolidates distributor pricing, design considerations, and replacement guidance for engineers maintaining or designing new APEX 20KC-based systems. Where current-generation Intel/Altera Agilex or Stratix devices are preferred for new designs, this datasheet remains the authoritative source for legacy support.
Drop-in alternatives for EP20K600CF672C-8 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672C-8 (same form factor and footprint) — differing in Process Technology, Speed Grade, Operating Temperature, Package, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672C-7
✅ Drop-In✓ In Stock
$1620 / Unit
View Datasheet →EP20K600CF672C-7ES
✅ Drop-In✓ In Stock
$2050 / Unit
View Datasheet →EP20K400CF672C-8
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP20K600CB672C8
✅ Drop-In✓ In Stock
$245 / Unit
View Datasheet →EP20K600CB672C8N
✅ Drop-In✓ In Stock
$69 / Unit
View Datasheet →EP20K600CF672C-8 Maximum Ratings & Electrical Characteristics
| Series | APEX 20KC |
| Device Type | FPGA (Field Programmable Gate Array) |
| Typical Gates | 600,000 |
| Logic Elements (LEs) | 24,320 |
| Embedded Memory Bits | 311,296 |
| Maximum User I/Os | 508 |
| Number of Pins | 672 |
| Package Type | 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) |
| Speed Grade | -8 |
| Propagation Delay (tPD) | 1.48 ns |
| Process Technology | 0.15 micrometer all-layer copper-metal |
| Architecture | MultiCore (LUT logic + embedded memory) |
| Operating Temperature Range | 0C to +85C (commercial) |
| Supply Voltage | Multi-rail (core + I/O banks) |
| Configuration Method | Serial / parallel / JTAG |
| Pin Compatibility | Pin-compatible with APEX 20KE family |
EP20K600CF672C-8 672-bga (fineline bga, 1.27 mm pitch, 45 x 45 mm) Pin Configuration Guide
Pin configuration for EP20K600CF672C-8 (672-bga (fineline bga, 1.27 mm pitch, 45 x 45 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672C-8.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672C-8 is suitable for 7 applications: Telecom Backplane Glue Logic, PCI Bus Bridge / Controller, High-Speed Datapath for Test & Measurement, Video Processing Pipeline, Network Switch Fabric Adaptation, ASIC Prototyping for Communications ASICs, Legacy Parallel-Bus Replacement.
Telecom Backplane Glue Logic
The EP20K600CF672C-8 fits telecom backplane glue logic because it delivers 508 user I/Os and 24,320 LEs that can absorb wide parallel bus bridging, framing, and protocol adaptation in a single device. Its MultiCore architecture combining LUT logic with 311,296 embedded memory bits enables distributed FIFOs and CRC engines alongside glue logic. With LVTTL, LVCMOS, GTL+, and SSTL-2/3 support, it bridges legacy 5 V bus segments to modern 3.3 V or 2.5 V ASICs on the same backplane. The 672-BGA exposes enough pins for 32-bit datapaths plus parity, control, and JTAG.
Recommended
PCI Bus Bridge / Controller
The EP20K600CF672C-8 is well suited for PCI bus bridge and controller designs because it includes PCI-compliant I/O buffers and 508 user I/Os, enough to implement 32-bit/33 MHz PCI targets with sideband signals. Its 600K-gate capacity absorbs transaction-layer state machines, scatter-gather DMA engines, and configuration-space registers in one device. The 311,296 embedded memory bits support posted-write buffers and read-retry queues. With 1.48 ns tPD the -8 speed grade meets PCI 33 MHz timing with comfortable margin.
Recommended
High-Speed Datapath for Test & Measurement
For test and measurement instrumentation the EP20K600CF672C-8 implements wide parallel acquisition datapaths because 508 user I/Os can directly interface LVDS or LVPECL ADC banks without external transceivers. The 24,320 LEs deliver register-rich FIR filters, FFT butterflies, and trigger logic at sample rates above 200 MHz. With 311,296 embedded memory bits, deep capture buffers and correlation RAM sit on-chip. Designers favor the -8 speed grade to push the critical path of pipelined stages tight.
Recommended
Video Processing Pipeline
The EP20K600CF672C-8 fits video processing pipelines because its 600K-gate density and 311,296 embedded memory bits support horizontal scalers, color-space converters, and frame buffers on a single die. The 508 user I/Os accommodate 30-bit digital RGB plus control signals from BT.656/BT.1120 sources. The MultiCore architecture allows pipeline parallelism where each LE column processes one tap, while the embedded system blocks store line delays. LVDS support simplifies direct connection to modern video ADCs.
Recommended
Network Switch Fabric Adaptation
The EP20K600CF672C-8 enables switch fabric adaptation because its 508 user I/Os can land multiple gigabit SERDES lanes via external PHYs while the on-chip fabric performs queueing, header parsing, and priority scheduling. The 24,320 LEs absorb TCAM-like lookup logic with parallel match logic, and the 311,296 embedded bits hold packet descriptors and statistics counters. GTL+ and SSTL-2/3 I/O standards ease interfacing to legacy switch ASICs.
Recommended
ASIC Prototyping for Communications ASICs
The EP20K600CF672C-8 is a strong ASIC prototyping vehicle because it provides 600K gates with 508 user I/Os and MultiCore architecture that closely matches the eventual ASIC implementation. Designers can validate RTL at near-ASIC speeds, prototype multiple clock domains, and reuse the same board for incremental revisions. The pin-compatible APEX 20KE footprint lets teams swap density grades without PCB rework. With commercial 0C to +85C operation it suits lab and bench bring-up.
Recommended
Legacy Parallel-Bus Replacement
The EP20K600CF672C-8 replaces aging parallel-bus ASICs and discrete TTL because its 508 I/Os absorb wide bus transceivers, parity generators, and address-decode logic in one device. Its 311,296 embedded memory bits support posted-write buffers and burst FIFOs that previously required external SRAM. The 1.48 ns tPD meets legacy bus timing budgets where modern FPGAs would be overkill. Pin compatibility with APEX 20KE allows migration from 20KE designs.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672C-8 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672C-7 | EP20K600CF672C-7ES | EP20K400CF672C-8 | EP20K600CB672C8 | EP20K600CB672C8N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-BGA (FineLine BGA, 1.27 mm) | 672-BGA - same | 672-BGA - same | 672-BGA - same | 672-BGA - same | 672-BGA - same |
| Typical Gates | 600,000 | 600,000 | 600,000 | 400,000 | 600,000 | 600,000 |
| Logic Elements | 24,320 | 24,320 | 24,320 | 16,640 | 24,320 | 24,320 |
| Speed Grade | -8 | -7 (slower) | -7 ES (slower) | -8 | -8 | -8 |
| Propagation Delay (tPD) | 1.48 ns | 1.68 ns | 1.68 ns | 1.48 ns | 1.48 ns | 1.48 ns |
| Max User I/Os | 508 | 508 | 508 | 488 | 508 | 508 |
| Embedded Memory Bits | 311,296 | 311,296 | 311,296 | 212,992 | 311,296 | 311,296 |
| Operating Temperature | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Same die, different speed grade - higher fMAX than EP20K600CF672C-7 (vs EP20K600CF672C-7)
- Twice the logic density vs APEX 20K400 series in same package (vs EP20K400CF672C-8)
- PCI-compliant I/O buffers integrated on-die (vs EP20K600CB672C8)
- Lead-free (N suffix) variant available for RoHS-rebuild programs (vs EP20K600CB672C8N)
Design Notes
The APEX 20KC requires multiple supply rails (VCCINT for core, VCCIO banks for I/O, VCCP for PCI) that must be sequenced with VCCINT leading or following VCCIO within the datasheet-specified window. Decouple each rail with 0.1 microfarad ceramic capacitors placed as close to the BGA balls as possible, and add bulk tantalum or polymer capacitors near the device. Because the part is obsolete, source decoupling recommendations from the original APEX 20KC datasheet, not from modern Agilex guidance, which has different rail names.
The 672-ball FineLine BGA at 1.27 mm pitch requires microvia or via-in-pad PCB technology for reliable breakout. Use a 1-2-1 or 1-2-3-2 build-up stackup with the outermost layer dedicated to signal escape and inner layers for power planes. Maintain at least 8 mil trace width on escape routes and avoid routing long parallel traces between balls to prevent crosstalk at the -8 speed grade. Reference the APEX 20KC development kit PCB layout for proven escape patterns.
At the -8 speed grade, treat 508 user I/Os as high-speed signals and apply 50 ohm controlled impedance on LVTTL/LVCMOS outputs and 100 ohm differential on LVDS/LVPECL pairs. Use IBIS models from Altera (now archived at Intel) for SI simulation, especially for PCI-compliant I/O. Series-damping resistors are recommended when driving long traces or backplane connectors to suppress ringing on the 1.48 ns tPD edge rates.
The FineLine BGA exposes the die through the thermal pad array, so a heatsink with thermal interface material is required for designs that sustain high toggle rates. With 0.15 micrometer copper process and 600K gates, typical junction-to-ambient theta_JA is approximately 12 to 18 C/W depending on PCB copper content; estimate 5W worst-case dissipation for a fully loaded design and verify with a thermal camera during bring-up. Place four thermistors near the BGA corners for temperature monitoring.
Do not assume JTAG chain order is portable from APEX 20KE to APEX 20KC designs - the BSDL files differ. Do not migrate from a -8 design to a -7 or -7ES speed grade without re-running static timing analysis, because tPD shifts from 1.48 ns to 1.68 ns may break critical paths. Do not exceed 3.3 V on VCCIO banks configured for LVTTL without derating, and avoid mixing 5 V and 3.3 V I/O standards on the same bank unless the bank supports the required VREF.
Compliance Information
RoHS and lead-free status not present in the verified web data. Lead-free N-suffix variants (e.g., EP20K600CB672C8N) likely exist per Altera naming convention but are not explicitly confirmed. APEX 20KC is not AEC-Q100 qualified - this is a commercial-grade FPGA family.
