EP20K60EFC324-3N vs EP20K60EFC324-2N Comparison
Detailed side-by-side comparison of EP20K60EFC324-3N by Altera and EP20K60EFC324-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K60EFC324-3N | EP20K60EFC324-2N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $35.40 | $52.73 |
| Series | APEX-20KE | APEX-20KE |
| Number of Logic Elements | 2560 Cells | β |
| Total Gates | 60K Gates (60000 typical) | β |
| Number of User I/Os | 196 | β |
| Package / Case | 324-BGA / 324-FBGA (19x19) | 324-BGA (FineLine BGA, 19x19 mm) |
| Supplier Device Package | 324-FBGA (19x19) | 324-FBGA (19x19) |
| Core Supply Voltage | 1.71V ~ 1.89V (1.8V nominal) | β |
| Operating Temperature | 0Β°C ~ 85Β°C (TJ) | β |
| Maximum Internal Frequency | 182 MHz (-3 speed grade) | β |
| Process Technology | 0.22 um CMOS | 0.22 Β΅m CMOS |
| Number of Pins | 324 | β |
| Mounting Type | Surface Mount | Surface Mount |
| Total RAM Bits | [DATA_NEEDED: total RAM bits per APEX 20K datasheet] | 32,768 |
| Embedded System Blocks | [DATA_NEEDED: ESB count] | β |
| I/O Standards Supported | [DATA_NEEDED: I/O standards list] | β |
| RoHS Status | [DATA_NEEDED: explicit RoHS statement] | unknown |
| Packaging | Bulk (per distributor listing) | β |
| Ordering Suffix | -N suffix ordering variant | β |
| Family | β | APEX 20K |
| Number of Logic Elements/Cells | β | 2,560 |
| Total System Gates | β | 60,000 |
| Number of Logic Array Blocks (LABs/CLBs) | β | 2,560 |
| Number of I/O | β | 196 |
| Core Voltage Supply | β | 1.71 V to 1.89 V (1.8 V typ.) |
| Internal Frequency (max) | β | 200 MHz |
| Propagation Delay | β | 1.72 ns |
| Operating Temperature Range (TJ) | β | 0 Β°C to 85 Β°C (commercial) |
| Architecture | β | MultiCore (LUT + ESB memory + product-term) |
| Configuration Method | β | Passive Serial / JTAG (IEEE 1149.1) |