EP2A15B724C9 vs EP2A15B724C Comparison
Detailed side-by-side comparison of EP2A15B724C9 by Intel and EP2A15B724C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A15B724C
EP2A15B724C - APEX II 15K LEs FPGA, 724-BGA | Altera (Intel)
EP2A15B724C ObsoleteSpecification Comparison
| Parameter | EP2A15B724C9 | EP2A15B724C |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $268.50 | $195.00 |
| Series | APEX II | β |
| Family | APEX II (EP2A15) | APEX II |
| Logic Elements | 16640 | β |
| Number of Gates | 600000 | β |
| Embedded Memory (RAM bits) | 425984 | β |
| User I/O Count | 492 | β |
| Supply Voltage (Core) | 1.5 V | β |
| I/O Voltages Supported | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) | β |
| Process Technology | 0.15 Β΅m all-layer copper (up to 8 metal layers) | 0.18 micron CMOS |
| Maximum Internal Frequency | 500 MHz | β |
| LVDS Data Rate | Up to 1 Gbps (True-LVDS) | β |
| Interface Standards | LVDS, LVPECL, PCML, HyperTransport | β |
| Embedded Memory Type | ESB - dual-port RAM / ROM / FIFO / CAM | β |
| Clock Management | On-chip PLLs | β |
| Package | 724-ball FCBGA (Fine-pitch Chip-Scale BGA) | 724-Ball FCBGA (FineLine BGA) |
| Operating Temperature | Commercial (0 Β°C to +85 Β°C) | [DATA_NEEDED: operating temperature grade] |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements (LEs) | β | 16,640 |
| Maximum User I/O Pins | β | 492 |
| Embedded RAM | β | 425,984 bits |
| Maximum System Gates | β | Up to 1.5M gates (family-level) |
| Embedded System Blocks (ESBs) | β | Configurable as dual-port RAM / ROM / FIFO |
| Interconnect | β | MultiTrack, deterministic |
| I/O Standards | β | LVTTL, LVCMOS, LVDS, PCI, GTL+ (family-level) |
| PLLs | β | Yes (family-level, up to 4 per device) |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Speed Grade | β | C (per suffix; specific speed bin [DATA_NEEDED]) |
| JTAG / Configuration | β | IEEE 1149.1 JTAG; passive serial / PS configuration supported (family-level) |