EP2A15B724C9 vs EP2A15F672C9 Comparison
Detailed side-by-side comparison of EP2A15B724C9 by Intel and EP2A15F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A15B724C9 | EP2A15F672C9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $268.50 | $175.00 |
| Series | APEX II | β |
| Family | APEX II (EP2A15) | β |
| Logic Elements | 16640 | 16640 |
| Number of Gates | 600000 | β |
| Embedded Memory (RAM bits) | 425984 | β |
| User I/O Count | 492 | β |
| Supply Voltage (Core) | 1.5 V | β |
| I/O Voltages Supported | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) | β |
| Process Technology | 0.15 Β΅m all-layer copper (up to 8 metal layers) | 0.15 Β΅m all-layer copper (up to 8 metal layers) |
| Maximum Internal Frequency | 500 MHz | 379 MHz |
| LVDS Data Rate | Up to 1 Gbps (True-LVDS) | β |
| Interface Standards | LVDS, LVPECL, PCML, HyperTransport | β |
| Embedded Memory Type | ESB - dual-port RAM / ROM / FIFO / CAM | β |
| Clock Management | On-chip PLLs | β |
| Package | 724-ball FCBGA (Fine-pitch Chip-Scale BGA) | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Operating Temperature | Commercial (0 Β°C to +85 Β°C) | 0 Β°C to 85 Β°C (commercial) |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Logic Family | β | APEX II (CMOS) |
| Usable Gates | β | 600 K |
| Macrocells | β | 1664 |
| Maximum User I/Os | β | 492 |
| Core Supply Voltage | β | 1.5 V |
| I/O Supply Voltage | β | 3.3 V |
| Propagation Delay | β | 1.94 ns |
| High-Speed I/O Support | β | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Embedded Memory | β | ESB dual-port RAM / FIFO |
| Configuration Interface | β | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | β | On-chip PLLs for clock synthesis and deskew |
| Compliance | β | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |