EP2A25F672I8N vs EP2A25F672I8 Comparison
Detailed side-by-side comparison of EP2A25F672I8N by Intel and EP2A25F672I8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A25F672I8N - APEX II FPGA 900K Gates 672-BGA | Intel / Altera
EP2A25F672I8N β Last Time BuySpecification Comparison
| Parameter | EP2A25F672I8N | EP2A25F672I8 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $198.50 | $125.00 |
| Family | APEX II | APEX II |
| Device | EP2A25 | β |
| Logic Elements | 24,320 | β |
| Gates | 900,000 | β |
| Embedded Memory (bits) | 622,592 | β |
| User I/Os | 492 | 492 |
| Package | 672-ball FC-FBGA (FineLine BGA) | 672-ball FC-FBGA (FineLine BGA), 27 Γ 27 mm, 1 mm pitch |
| Package Size | 27 x 27 mm | β |
| Ball Pitch | 1 mm | β |
| Process Technology | 0.15 Β΅m all-layer copper-metal | 0.15 Β΅m CMOS, up to 8 metal layers |
| Metal Layers | Up to 8 | β |
| Core Voltage (VCCINT) | 1.5 V | β |
| Internal Frequency (max) | 333 MHz | β |
| Propagation Delay | 1.69 ns | 1.69 ns (typical) |
| Operating Temperature | 0 Β°C to 85 Β°C | β40 Β°C to +85 Β°C (industrial, 'I' grade) |
| Logic Family | CMOS | β |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI |
| Configuration Method | SRAM-based (Altera Quartus II) | β |
| RoHS Status | unknown | unknown |
| Lead-Free | unknown | β |
| Logic Elements / Cells | β | 24,320 |
| Equivalent Gates | β | 900,000 |
| Embedded Memory (RAM bits) | β | 622,592 |
| Number of PLLs | β | 4 |
| Core Supply Voltage | β | 1.5 V |
| Internal Performance | β | 333 MHz (per legacy datasheet) |
| LVDS / High-Speed I/O | β | Yes, up to 1 Gbps |
| Mounting Type | β | Surface Mount (BGA) |
| Speed Grade | β | I8 (industrial, 8-speed-grade per APEX II ordering scheme) |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |
| Lead-Free Status | β | unknown |