EP2A40F672C6N vs EP2A40F672C9 Comparison
Detailed side-by-side comparison of EP2A40F672C6N by Intel and EP2A40F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A40F672C9
EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera
EP2A40F672C9 β Last Time BuySpecification Comparison
| Parameter | EP2A40F672C6N | EP2A40F672C9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $165.00 | $62.00 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | β |
| Maximum System Gates | 1,125,000 | β |
| Embedded RAM Bits | 442,368 | β |
| Embedded System Blocks (ESBs) | 160 | β |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | β |
| Core Voltage | 1.5 V | 1.5 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | True-LVDS, LVPECL, PCML, HyperTransport |
| Package | 672-ball FineLine BGA | 672-BBGA, FC-FBGA (FineLine) |
| Operating Temperature | Commercial (0C to +85C) | 0 Β°C to 85 Β°C (commercial) |
| Speed Grade | C6 (per part number suffix) | β |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 Β΅m all-layer copper, up to 8 metal layers |
| PLL Count | [DATA_NEEDED: PLL count] | β |
| Device Family | β | APEX II PLD |
| Logic Elements / Cells | β | 38,400 |
| System Gates | β | 1.5 M |
| Macros | β | 2,560 |
| User I/Os | β | 492 |
| Number of Pins | β | 672 |
| Package Size | β | 27 mm Γ 27 mm, 1 mm ball pitch |
| Logic Family | β | CMOS |
| Propagation Delay | β | 1.55 ns |
| Internal Speed Grade | β | 366 MHz |