EP2A70B724I-8 vs EP2A70B724C8N Comparison
Detailed side-by-side comparison of EP2A70B724I-8 by Altera and EP2A70B724C8N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel
EP2A70B724C8N β Last Time BuySpecification Comparison
| Parameter | EP2A70B724I-8 | EP2A70B724C8N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $119.00 | $240.00 |
| Family | APEX II | FPGA (PLD) |
| Logic Elements / Cells | 67,200 cells | 67,200 |
| System Gates | 3,000,000 | 3,000,000 (3 M) |
| Maximum Internal Frequency | 281 MHz | β |
| Process Technology | 0.15 Β΅m CMOS | 0.15 um CMOS, SRAM-based |
| Core Supply Voltage | 1.5 V | 1.5 V |
| I/O Supply Voltage | 3.3 V | β |
| Number of Pins | 724 | β |
| Package Type | FCBGA (Flip-Chip Ball Grid Array) | FCBGA-724 (square) |
| Operating Temperature | -40 Β°C to +100 Β°C (Industrial) | β |
| Peak Reflow Temperature | 220 Β°C (per JEDEC J-STD-020) | β |
| User I/O Banks | [DATA_NEEDED: user I/O bank count] | β |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | β |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | β |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | β |
| Embedded RAM | [DATA_NEEDED: total bits] | β |
| PLLs | [DATA_NEEDED: PLL count] | β |
| Configuration Method | JTAG / Passive Serial / Passive Parallel | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | β |
| Series | β | APEX II (EP2A70) |
| Macrocells | β | 16 |
| Product Terms | β | 32 |
| Propagation Delay | β | 2.49 ns |
| Maximum Internal Clock Frequency | β | 281 MHz |
| Maximum Clock Frequency (fMAX) | β | 1694.91 MHz |
| Architecture | β | PLA-type / LUT-based |
| Number of Pins / Balls | β | 724 |
| Terminal Pitch | β | 1.270 mm |
| Maximum User I/O | β | 536 |