EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel
MPN: EP2A70B724C8N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $385 | $385.00 |
| 10 | $345 | $3,450.00 |
| 100 | $295 | $29,500.00 |
| 500 | $265 | $132,500.00 |
| 1,000 | $240 | $240,000.00 |
EP2A70B724C8N Overview
An FPGA (Field-Programmable Gate Array) is a reconfigurable semiconductor device that integrates configurable logic blocks, programmable interconnect, and embedded memory into a single die. Within the broader taxonomy, the EP2A70B724C8N belongs to the PLD (programmable logic device) family, which encompasses CPLDs and FPGAs; within Altera's portfolio it sits in the APEX II series, a high-density, SRAM-based, look-up-table (LUT) architecture targeting data-path, communications, and DSP workloads.
Key features of this device include a 2.49 ns propagation delay, 16 embedded macrocells per logic array block with 32 product terms, 536 maximum user I/O lines, 1.270 mm ball pitch, and a square 724-terminal FCBGA package optimized for high-speed signal integrity. The APEX II architecture combines LUT-based logic with embedded array blocks (EABs) for distributed RAM and DSP, enabling on-chip implementation of multipliers, FIFOs, and dual-port memories without external components.
Typical applications for the EP2A70B724C8N include high-throughput telecommunications line cards, baseband signal processing, networking switches and routers, custom DSP pipelines, and prototyping for ASIC-class designs. The 724-pin FCBGA and 1.5 V core make it suitable for high-density boards with multiple supply rails.
When designing with this device, ensure decoupling capacitors are placed adjacent to every supply pin and that the 1.5 V core rail is generated by a low-noise LDO or DC-DC converter with adequate transient response. Note that the APEX II family has been classified as mature/end-of-life by Altera/Intel; confirm long-term availability before committing to new production designs.
This page synthesizes distributor pricing, drop-in same-package APEX II variants, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP2A70B724C8N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2A70B724C8N (same form factor and footprint) — differing in Process Technology, Package, Operating Temperature, Maximum Internal Frequency, Speed Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2A70B724C8
✅ Drop-In✓ In Stock
$1250 / Unit
View Datasheet →EP2A70B724C7N
✅ Drop-In✓ In Stock
$188 / Unit
View Datasheet →EP2A70B724C7
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP2A70B724C7ES
✅ Drop-In✓ In Stock
$2190 / Unit
View Datasheet →EP2A40B724C8N
✅ Drop-In✓ In Stock
$199.5 / Unit
View Datasheet →EP2A40B724C8
✅ Drop-In✓ In Stock
$615 / Unit
View Datasheet →EP2A40FB724C8
✅ Drop-In✓ In Stock
$205 / Unit
View Datasheet →EP2A70B724C8N Maximum Ratings & Electrical Characteristics
| Series | APEX II (EP2A70) |
| Family | FPGA (PLD) |
| System Gates | 3,000,000 (3 M) |
| Logic Elements / Cells | 67,200 |
| Macrocells | 16 |
| Product Terms | 32 |
| Propagation Delay | 2.49 ns |
| Maximum Internal Clock Frequency | 281 MHz |
| Maximum Clock Frequency (fMAX) | 1694.91 MHz |
| Process Technology | 0.15 um CMOS, SRAM-based |
| Core Supply Voltage | 1.5 V |
| Architecture | PLA-type / LUT-based |
| Package Type | FCBGA-724 (square) |
| Number of Pins / Balls | 724 |
| Terminal Pitch | 1.270 mm |
| Mounting Type | Surface Mount (BGA) |
| Maximum User I/O | 536 |
EP2A70B724C8N Pin Configuration
| Pin B1 | I/O — User I/O ball (FPGA user I/O bank) |
| Pin B2 | VCCINT — Core supply (1.5 V) |
| Pin B3 | GND — Ground |
| Pin B4 | I/O — User I/O ball |
| Pin B5 | I/O — User I/O ball |
| Pin B6 | I/O — User I/O ball |
| Pin B7 | VCCIO — I/O supply (2.5 V / 3.3 V) |
| Pin B8 | I/O — User I/O ball |
| Pin B9 | I/O — User I/O ball |
| Pin B10 | GND — Ground |
| Pin B11 | I/O — User I/O ball |
| Pin B12 | I/O — User I/O ball |
| Pin B13 | I/O — User I/O ball |
| Pin B14 | VCCINT — Core supply (1.5 V) |
| Pin B15 | I/O — User I/O ball |
| Pin B16 | I/O — User I/O ball |
| Pin B17 | GND — Ground |
| Pin B18 | I/O — User I/O ball |
| Pin B19 | I/O — User I/O ball |
| Pin B20 | I/O — User I/O ball |
| Pin B21 | VCCINT — Core supply (1.5 V) |
| Pin B22 | I/O — User I/O ball |
| Pin B23 | I/O — User I/O ball |
| Pin B24 | GND — Ground |
| Pin B25 | I/O — User I/O ball |
| Pin B26 | I/O — User I/O ball |
| Pin B27 | I/O — User I/O ball |
| Pin B28 | VCCIO — I/O supply |
| Pin B29 | I/O — User I/O ball |
| Pin B30 | I/O — User I/O ball |
| Pin C1 | TCK — JTAG test clock (boundary scan) |
| Pin C30 | TMS — JTAG test mode select |
| Pin D1 | TDI — JTAG test data in |
| Pin D30 | TDO — JTAG test data out |
| Pin AA1 | MSEL0 — Configuration mode select 0 |
| Pin AA30 | MSEL1 — Configuration mode select 1 |
| Pin AB1 | nSTATUS — Configuration status (active low) |
| Pin AB2 | nCONFIG — Configuration control (active low) |
| Pin AB3 | DCLK — Configuration clock |
| Pin AB4 | DATA0 — Configuration data input |
Typical Applications
EP2A70B724C8N is suitable for 6 applications: Telecommunications Line Card Processing, High-Speed Networking Switch / Router, DSP and Digital Filter Implementation, ASIC Prototyping and Emulation, Industrial Imaging and Machine Vision, Legacy Avionics and Defense Signal Processing.
Telecommunications Line Card Processing
The EP2A70B724C8N's 3M system gates and 67,200 logic elements make it ideal for telecom line cards implementing multi-channel framer, mapper, and forward-error-correction (FEC) functions. Its 281 MHz internal clock supports high-speed serial protocol glue logic, while the 536 user I/O lines accommodate parallel backplane interfaces and external memory buses (DDR, QDR SRAM). Place the device on a 1.5 V LDO-fed core rail and pair with a MAX II configuration device to load SRAM-based bitstream at every power-up. The 724-FCBGA footprint also enables short trace lengths to high-speed SerDes transceivers for line-side interfaces.
Recommended
High-Speed Networking Switch / Router
The EP2A70B724C8N is well suited to custom switching fabrics and packet-processing pipelines because of its LUT-rich architecture, embedded array blocks (EABs) for distributed CAM/RAM tables, and 536 user I/O for parallel interconnect. Its 2.49 ns propagation delay enables fast combinational paths for header parsing and queue management. Use the device to implement custom lookup engines, traffic-shaping logic, and MAC/PHY bridging glue between switching ASICs. Ensure the 1.5 V core rail has at least 1 A of headroom and place high-frequency decoupling within 5 mm of every supply ball.
Recommended
DSP and Digital Filter Implementation
Engineers implementing high-throughput FIR filters, FFT engines, and digital down-converters benefit from the EP2A70B724C8N's 3M gates and embedded array blocks, which provide on-chip distributed RAM and dedicated carry chains for multiplier-accumulator pipelines. With a 281 MHz internal clock, the device can realize multi-channel baseband processing at sample rates well above 100 MHz. Pair the FPGA with external SDRAM/DDR for coefficient storage; the 724-FCBGA footprint exposes ample user I/O for parallel memory buses and high-speed serial links to DAC/ADC converters.
Recommended
ASIC Prototyping and Emulation
The EP2A70B724C8N is widely used to prototype and emulate ASIC designs before tape-out because of its large gate capacity, fast compile times in Altera Quartus II software, and JTAG-based debug support. The 724-ball FCBGA exposes 536 user I/O for connecting to ASIC pin maps, and the SRAM-based fabric supports unlimited reprogramming cycles. For multi-FPGA emulation platforms, the 1.5 V core and standardized FCBGA-724 footprint enable repeatable PCB builds. Verify Quartus II version compatibility because the APEX II family requires legacy software toolchains.
Recommended
Industrial Imaging and Machine Vision
Camera-link and CoaXPress interface bridges, real-time image preprocessing, and high-speed frame-buffer management can all be implemented on the EP2A70B724C8N. Its 67,200 logic elements support multi-tap pipelined image processing at 281 MHz, while 536 user I/O accommodate parallel LVDS data streams from CMOS image sensors. Use the device's embedded RAM blocks for line-buffer and frame-buffer storage, and pair it with external DDR memory for higher resolution processing. The 1.5 V core and industrial temperature grade make it suitable for factory-floor deployments.
Recommended
Legacy Avionics and Defense Signal Processing
The EP2A70B724C8N's mature qualification status makes it attractive for defense and avionics upgrades where re-qualifying an entire board design is prohibitively expensive. Its 3M gates can host multi-channel radar DSP, electronic-countermeasure (ECM) algorithms, and legacy MIL-STD-1553 bridges. The 724-ball FCBGA package and 1.5 V core suit ruggedized boards with controlled-impedance stack-ups. Verify availability through authorized defense distributors because the APEX II family is in last-time-buy status and long lead times are common.
Recommended
Recommended Products Summary
Engineering reference data for EP2A70B724C8N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2A70B724C8 | EP2A70B724C7N | EP2A70B724C7 | EP2A40B724C8N |
|---|---|---|---|---|---|
| Package | FCBGA-724 (1.270 mm pitch) | FCBGA-724 - same | FCBGA-724 - same | FCBGA-724 - same | FCBGA-724 - same |
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Series / Family | APEX II (EP2A70) | APEX II (EP2A70) | APEX II (EP2A70) | APEX II (EP2A70) | APEX II (EP2A40) |
| System Gates | 3 M | 3 M (same die) | 3 M | 3 M | 2 M (-33%) |
| Logic Elements / Cells | 67,200 | 67,200 | 67,200 | 67,200 | 40,000 (-40%) |
| Speed Grade | C8 | C8 | C7 (slower) | C7 | C8 |
| Maximum Internal Clock | 281 MHz | 281 MHz | ~250 MHz | ~250 MHz | 281 MHz (same speed grade) |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Package Suffix (N) | Yes (Pb-free lead-free) | No | Yes | No | Yes |
Key Differentiators
- Highest-density APEX II die in 724-FCBGA (vs EP2A40B724C8N)
- Faster speed grade within APEX II family (vs EP2A70B724C7N)
- Pb-free N-suffix variant (vs EP2A70B724C8 (non-N))
Design Notes
Estimated: At typical operating conditions, the EP2A70B724C8N 1.5 V core draws approximately 0.5-1.2 A depending on toggle rate and resource utilization; design the core LDO for at least 1.5 A continuous with 100 mV maximum dropout under transient load. Place a 220 uF bulk tantalum plus 22 uF ceramic on the 1.5 V rail within 25 mm of the FCBGA supply balls, and add 0.1 uF X7R decouplers adjacent to every supply pin to control simultaneous-switching-noise (SSN) on the 724-ball matrix.
Estimated: With theta_JA around 12-15 C/W on a 1 oz 4-layer FCBGA-724 board, the EP2A70B724C8N dissipating 3 W yields a junction temperature rise of 36-45 C above ambient. For industrial-temperature (-40 C to +100 C) operation, ensure ambient stays below 70 C with adequate airflow (200 LFM minimum) and thermal vias beneath the exposed die pad. Consider a heatsink with thermal interface material when sustained utilization exceeds 70%.
The 724-ball FCBGA at 1.270 mm pitch requires a PCB stack-up with 6-8 layers and microvia (laser-drilled) technology for breakout routing; standard 0.2 mm trace/space rules apply on outer layers. Use dog-bone fanout on inner layers or via-in-pad for power/ground. Escape routing on the top layer should leave 2-3 mm of continuous ground plane beneath the BGA for return-path integrity. Follow JEDEC J-STD-020 MSL3 handling procedures - the FCBGA package is moisture-sensitive and requires dry-pack storage.
Do not confuse the EP2A70B724C8N (APEX II, 3M gates, 1.5 V) with the EP20K600CF672 (APEX 20K, 600k gates, different package and voltage). The APEX II family requires Quartus II version 9.0 or earlier because Altera dropped support after the Intel acquisition - keep legacy toolchains archived. Configuration requires an external serial flash (EPCQ64ASI16N recommended) for SRAM-based bitstream; the device will not retain logic on power-down.
Compliance Information
RoHS compliant per Altera/Intel product declaration. N-suffix variant is Pb-free and RoHS-compliant. AEC-Q100 not applicable for this industrial/communications FPGA. Lifecycle status: last-time-buy - confirm availability before new production designs.
