EP2C50F672C8N vs EP2C50F672I8N Comparison
Detailed side-by-side comparison of EP2C50F672C8N by Intel and EP2C50F672I8N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2C50F672C8N - Cyclone II FPGA, 50K LE, 672-BGA | Intel / Altera
EP2C50F672C8N β Last Time BuySpecification Comparison
| Parameter | EP2C50F672C8N | EP2C50F672I8N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $148.75 | $248.42 |
| Series | Cyclone II | β |
| Number of Logic Elements | 50,528 | β |
| Number of Logic Array Blocks (LABs) | 4,608 | β |
| Total RAM Bits | 594,432 | β |
| Number of I/O | 450 | β |
| Number of User I/O Banks | 8 (per family architecture) | β |
| Number of PLLs | 4 | β |
| Number of DLLs | 2 | β |
| Embedded 18x18 Multipliers | 86 | β |
| Core Voltage | 1.2 V | β |
| Package | 672-FBGA (FineLine BGA) | β |
| Package Body Size | 27 mm x 27 mm | β |
| Mounting Type | Surface Mount | Surface mount BGA |
| Operating Temperature | 0C to +85C (commercial) | β |
| Speed Grade | C8 | β |
| Process Technology | 90 nm low-k CMOS | β |
| Configuration | JTAG + serial/parallel | β |
| RoHS Status | [DATA_NEEDED: rohs status from datasheet] | unknown |
| Product Type | β | Field Programmable Gate Array (FPGA) |
| Device Family | β | Cyclone II |
| Logic Technology | β | CMOS |
| Logic Elements | β | 50,528 |
| Embedded Memory | β | 594,432 bits |
| User I/O | β | 450 |
| Supply Voltage | β | 1.2 V |
| Package Type | β | 672-BGA |
| Package Designation | β | FBGA-672 |
| Pin Count | β | 672 |
| Ordering Temperature Grade | β | I8N industrial grade designation |
| Configuration Method | β | [DATA_NEEDED: configuration mode] |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Embedded Multipliers | β | [DATA_NEEDED: embedded multiplier count] |
| Phase-Locked Loops | β | [DATA_NEEDED: PLL count] |
| Global Clock Networks | β | [DATA_NEEDED: global clock network count] |
| REACH Status | β | unknown |