EP2S130F1020I4RB vs EP2S130F1020C5N Comparison
Detailed side-by-side comparison of EP2S130F1020I4RB by Intel and EP2S130F1020C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2S130F1020I4RB
EP2S130F1020I4RB - Stratix II FPGA 132540 Cells 1.2V FC-FBGA | Intel
EP2S130F1020I4RB ObsoleteIntel
EP2S130F1020C5N
EP2S130F1020C5N - Stratix II FPGA, 132K LEs, 1020-FBGA | Intel
EP2S130F1020C5N NrndSpecification Comparison
| Parameter | EP2S130F1020I4RB | EP2S130F1020C5N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $875.00 | $1,320.00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Number of User I/O | 742 | β |
| Number of Logic Gates | 6,747,840 (equivalent gates) | β |
| Operating Frequency (Max) | 711.24 MHz | β |
| Process Technology | 90 nm | 90 nm |
| Core Supply Voltage | 1.2 V | β |
| Package | 1020-pin FC-FBGA | 1020-ball FC-FBGA (33x33 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +100C (Industrial) | Commercial (0C to +85C, C5 grade) |
| Speed Grade | I4 | β |
| Number of Transceivers | 12 (up to 6.375 Gbps) | β |
| Embedded Memory | 6,747,840 bits (RAM blocks) | β |
| Number of PLLs | 4 (up to 16 clock pins) | β |
| Configuration Mode | JTAG / PS / PPS / EPCS / EPCQ | β |
| MSL Level | 3 | β |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: rohs status] |
| Adaptive Logic Modules (ALMs) | β | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | β | 6,747,840 bits |
| User I/Os | β | 734 |
| Core Supply Voltage (VCCINT) | β | 1.15 V to 1.25 V |
| Maximum Internal Frequency | β | 609.76 MHz |
| Temperature Grade | β | C5 (other - per Partstack) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| PLLs | β | 4 (typical Stratix II feature) |
| Global Clock Networks | β | 16 (typical Stratix II feature) |
| Configuration Method | β | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | β | Republic of Korea (per GlobalSpec) |
| ECCN | β | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | β | 2023 (per GlobalSpec) |