EP2S60F672C5 vs EP2S60F672C3 Comparison
Detailed side-by-side comparison of EP2S60F672C5 by Intel and EP2S60F672C3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S60F672C5 | EP2S60F672C3 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $410.85 | $1,033.14 |
| Family | Stratix II | Stratix II |
| Device Family | Stratix II FPGA | β |
| Logic Elements | 60,440 | 60,440 |
| Configurable Logic Blocks (CLBs) | 24,176 | β |
| Total RAM Bits | 2,544,192 bits | 2,544,192 |
| Maximum User I/Os | 492 | β |
| Operating Frequency | Up to 609.76 MHz | β |
| Core Voltage | 1.2 V | 1.2 V |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Package | 672-ball FC-FBGA (35 Γ 35 mm, 1 mm pitch) | 672-BBGA, FC-FBGA, 35 x 35 mm, 1.0 mm pitch |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C5 suffix) | β |
| Operating Temperature Range | 0Β°C to +85Β°C | β |
| Number of PLLs | 4 | β |
| DSP Blocks | 12 (dedicated 18 Γ 18 multipliers) | [DATA_NEEDED: DSP block count] |
| I/O Standards | LVDS, LVTTL, SSTL, HSTL, PCI-X | β |
| Configuration Scheme | Fast Passive Parallel, JTAG, Active Serial | β |
| RoHS Status | Non-RoHS (legacy product, pre-RoHS production runs) | [DATA_NEEDED: RoHS status] |
| Adaptive Logic Modules (ALMs) | β | [DATA_NEEDED: ALM count] |
| Embedded Multiplier Blocks | β | [DATA_NEEDED: 9x9 multiplier count] |
| User I/Os | β | 492 |
| PLLs | β | 4 |
| Global Clocks | β | [DATA_NEEDED: global clock count] |
| Speed Grade | β | C3 |
| Configuration Modes | β | PS, PPS, PPA, FPP, JTAG |
| Operating Temperature | β | 0C to +85C (commercial) |
| MSL Level | β | [DATA_NEEDED: MSL level] |