EP2S60F672C3 - Stratix II 60K LE FPGA, 672-BGA | Intel / Altera
MPN: EP2S60F672C3 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1721.89 | $1,721.89 |
| 10 | $1549.7 | $15,497.00 |
| 100 | $1377.51 | $137,751.00 |
| 500 | $1205.32 | $602,660.00 |
| 1,000 | $1033.14 | $1,033,140.00 |
EP2S60F672C3 Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic functionality is defined after manufacturing via a configuration bitstream, in contrast to an ASIC (Application-Specific Integrated Circuit) or a fixed-function ASSP. FPGAs occupy the role of programmable glue logic and parallel processing engines in modern electronic systems, sitting between general-purpose microcontrollers and hard-wired ASICs in the broader hierarchy: programmable logic device (PLD) -> CPLD -> FPGA -> SoC FPGA. Stratix II specifically is a high-performance, logic-rich family designed for ASIC prototyping, DSP, and communications infrastructure.
Key features of the EP2S60F672C3 include 60,440 logic elements (LEs), 2,544,192 RAM bits organized in TriMatrix memory blocks (MRAM, M512, M4K, M-RAM), up to 492 user I/Os supporting multiple I/O standards (LVTTL, LVCMOS, SSTL, HSTL, LVDS, PCI, PCI-X), and four enhanced phase-locked loops (PLLs) for clock management. The device supports configuration via passive serial (PS), passive parallel synchronous (PPS), passive parallel asynchronous (PPA), fast passive parallel (FPP), and JTAG modes, giving board designers flexibility for in-system programming or board-level configuration chains.
At the architecture level, the Stratix II family introduced an adaptive logic module (ALM) structure that significantly improves logic utilization compared with the 4-input LUT architecture of the original Stratix. The 1.2 V core supply combined with the 90 nm process node yields low static and dynamic power relative to the prior generation. Configuration bitstream encryption (AES) and on-chip termination (OCT) further reduce external component count, while the -C3 speed grade trades some Fmax for cost savings relative to the faster -C4 and -C5 grades.
Typical applications include ASIC prototyping and emulation, telecom and networking line cards, military and aerospace signal processing, high-performance DSP pipelines, broadcast video processing, and test-and-measurement instrumentation. The 672-BGA package supports the high I/O count required by memory-bus-intensive designs and parallel DSP datapaths.
A primary design consideration for the EP2S60F672C3 is that the 672-BGA with 1.0 mm pitch demands multilayer PCB fabrication with microvia technology; designers should plan for at least 6 PCB layers and controlled-impedance routing for high-speed I/O. Designers should also confirm supply longevity, as the Stratix II family is approaching end-of-life status with Intel's product discontinuance program.
This page synthesizes distributor pricing as of 2026-09-09, drop-in alternatives from the Stratix II family, and practical design guidance not found in the original Altera datasheet.
Drop-in alternatives for EP2S60F672C3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S60F672C3 (same form factor and footprint) β differing in Package, Speed Grade, RoHS Status, PLLs, Total RAM Bits.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S60F672C3N
β Drop-Inβ In Stock
$1175 / Unit
View Datasheet βEP2S60F672C4N
β Drop-Inβ In Stock
$325 / Unit
View Datasheet βEP2S60F672C5N
β Drop-Inβ In Stock
$170 / Unit
View Datasheet βEP2S60F672I5N
β Drop-Inπ Reference alternative (not in catalog)
EP2S30F672C3N
β Drop-Inβ In Stock
$55 / Unit
View Datasheet βEP2S30F672C3
β Drop-Inβ In Stock
$780 / Unit
View Datasheet βEP2S15F672C3N
β Drop-Inβ In Stock
$142.75 / Unit
View Datasheet βEP2S60F672C3 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 60,440 |
| Total RAM Bits | 2,544,192 |
| User I/Os | 492 |
| PLLs | 4 |
| Process Technology | 90 nm CMOS |
| Core Voltage | 1.2 V |
| Speed Grade | C3 |
| Package | 672-BBGA, FC-FBGA, 35 x 35 mm, 1.0 mm pitch |
| Mounting Type | Surface Mount |
| Configuration Modes | PS, PPS, PPA, FPP, JTAG |
| Operating Temperature | 0C to +85C (commercial) |
EP2S60F672C3 Pin Configuration
| Pin A1 | I/O β User I/O bank (function varies by pin-out file) |
| Pin A2 | I/O β User I/O bank |
| Pin A3 | I/O β User I/O bank |
| Pin A4 | I/O β User I/O bank |
| Pin A5 | VCCIO β I/O bank supply voltage |
| Pin A6 | GND β Ground |
| Pin A7 | I/O β User I/O bank |
| Pin A8 | I/O β User I/O bank |
| Pin B1 | GND β Ground |
| Pin B2 | I/O β User I/O bank |
| Pin B3 | I/O β User I/O bank |
| Pin B4 | I/O β User I/O bank |
| Pin B5 | I/O β User I/O bank |
| Pin B6 | I/O β User I/O bank |
| Pin B7 | I/O β User I/O bank |
| Pin B8 | VCCINT β Core supply 1.2 V |
Typical Applications
EP2S60F672C3 is suitable for 6 applications: ASIC Prototyping and Emulation, Telecommunications Line Cards, High-Performance DSP Pipelines, Broadcast Video Processing, Military and Aerospace Signal Processing, Test and Measurement Instrumentation.
ASIC Prototyping and Emulation
The EP2S60F672C3 fits ASIC prototyping because its 60,440 logic elements, 2,544,192 bits of embedded TriMatrix memory, and 492 user I/Os provide the capacity to map multi-million-gate ASIC designs onto a single device. The Stratix II adaptive logic module (ALM) architecture delivers an average 20 percent improvement in logic utilization over the prior 4-LUT architecture, so more of the user's RTL fits per device. Four PLLs and 16 global clock networks support the multi-clock-domain partitioning typical of large ASICs. The 672-BGA exposes enough I/O to break out the entire peripheral bus of the target ASIC for real-world interfacing. Engineers commonly chain multiple EP2S60 boards to prototype ASICs that exceed 60K LEs.
Recommended
Telecommunications Line Cards
The EP2S60F672C3 is widely deployed in telecom line-card designs where the combination of 60K LEs, 2.5 Mbit of fast on-chip memory, and 492 user I/Os enables packet processing, traffic shaping, and serializer/deserializer (SerDes) glue logic on a single chip. The TriMatrix memory architecture provides multiple block sizes (M512, M4K, M-RAM) that match the varied buffer sizes required by ATM, Ethernet, and SONET/SDH payload processing. The 90 nm process provides low static leakage for thermally constrained central-office environments. Designers use the four PLLs to derive multiple reference clocks from a single system clock while maintaining jitter below 1 ps RMS.
Recommended
High-Performance DSP Pipelines
The EP2S60F672C3 accelerates DSP pipelines in radar, software-defined radio, and baseband processing, where its embedded multiplier blocks and DSP blocks deliver hundreds of GMACs (multiply-accumulates per second). The 2,544,192 bits of on-chip memory act as coefficient and sample storage, eliminating the latency of off-chip SRAM access. Designers typically instantiate FIR filters, FFTs, and digital down-converters (DDCs) that benefit from the parallel hardware architecture. The 492 I/Os allow direct connection to high-speed A/D and D/A converters without external glue logic. Quartus II's DSP Builder toolchain maps MATLAB/Simulink designs directly to the multiplier fabric for rapid development.
Recommended
Broadcast Video Processing
The EP2S60F672C3 supports broadcast video processing workflows such as SD/HD/3G-SDI routing, de-interlacing, scaling, and color space conversion, where its 60K LEs and 2.5 Mbit memory are sufficient to handle 1080p60 video streams in real time. The 492 I/Os enable multi-channel SDI input/output with embedded audio extraction and re-insertion. The TriMatrix memory allows line buffers and frame stores without external SDRAM for many common operations. Designers use the four PLLs to generate pixel clocks at 74.25, 148.5, and 297 MHz for HD and UHD formats. Quartus II's Video and Image Processing (VIP) suite provides ready-made IP for the most common video functions.
Recommended
Military and Aerospace Signal Processing
The EP2S60F672C3 is used in military and aerospace applications including electronic warfare, radar signal processing, and secure communications, where the combination of moderate logic density, large on-chip memory, and high I/O count enables single-chip implementations of many sensor-processing functions. The industrial temperature variants (EP2S60F672I5N) operate from -40C to +100C, suitable for avionics and ground-vehicle environments. Designers use the configuration bitstream AES encryption to protect against reverse engineering of classified algorithms. The 672-BGA package with 1.0 mm pitch is compatible with mil-spec PCB fabrication guidelines used for ruggedized applications.
Recommended
Test and Measurement Instrumentation
The EP2S60F672C3 powers the digital back-end of high-end oscilloscopes, logic analyzers, and protocol analyzers, where the FPGA performs real-time triggering, decimation, and protocol decoding. The 2,544,192 bits of embedded memory act as deep acquisition memory, capturing pre-trigger samples at full sample rate without external buffer chips. The 492 I/Os route the digital data path from front-end A/D converters to display engines and trigger logic. The four PLLs generate multiple synchronized clocks for the sample rate, the display refresh, and the data-link transfer. The -C3 speed grade is sufficient for most instrumentation clocks below 400 MHz.
Recommended
Recommended Products Summary
Engineering reference data for EP2S60F672C3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S60F672C3N | EP2S60F672C4N | EP2S60F672C5N | EP2S30F672C3N |
|---|---|---|---|---|---|
| Package | 672-BBGA, FC-FBGA, 35x35 mm | 672-BBGA, FC-FBGA - same | 672-BBGA, FC-FBGA - same | 672-BBGA, FC-FBGA - same | 672-BBGA, FC-FBGA - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Speed Grade | C3 | C3 | C4 (Fmax +15-25%) | C5 (Fmax +25-40%) | C3 |
| Logic Elements | 60,440 | 60,440 | 60,440 | 60,440 | 30,220 |
| Total RAM Bits | 2,544,192 | 2,544,192 | 2,544,192 | 2,544,192 | 1,338,720 |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Process Node | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm |
| Lead-Free (N suffix) | No (no N suffix) | Yes | Yes | Yes | Yes |
Key Differentiators
- Highest logic density in the C3 speed grade within the Stratix II family (vs EP2S30F672C3N)
- Cost-optimized C3 speed grade (vs EP2S60F672C5N)
- Drop-in compatibility across the Stratix II 60K family (vs EP2S60F672C3N)
Design Notes
The EP2S60F672C3 at full utilization and typical clock rates consumes approximately 10 to 15 W of dynamic power, plus 0.5 to 1.5 W of static power due to the 90 nm process leakage. The 672-BGA has a theta_JA in the range of 8 to 12 C/W with a properly designed thermal pad pattern on the PCB, which allows a 30 C junction temperature rise over ambient. Use thermal vias under the central BGA balls and copper pours on inner layers to spread the heat. If the design runs at 100% utilization with a high toggle rate, active cooling (a small heatsink or low-velocity airflow) is recommended.
The 672-BGA with 1.0 mm pitch demands a multilayer PCB with microvia (laser-drilled or sequential lamination) technology; standard 8-mil via processes cannot reliably capture the 1.0 mm ball pitch. Use at least 6 PCB layers with a dedicated ground plane adjacent to the top BGA layer to provide a low-impedance return path. Match the BGA land pattern exactly to the IPC-7351 nominal recommendation and apply an NSMD (non-solder mask defined) pad with 0.5 mm clearance between adjacent pads. Place decoupling capacitors (0.1 uF and 0.01 uF) on the back side of the PCB directly under the BGA, stitched to inner power and ground planes.
The most common pitfalls when designing with the EP2S60F672C3 are: (1) assuming all 672 balls are user I/Os - many are dedicated configuration, clock, JTAG, or power pins, and the actual user I/O count is 492; (2) failing to include the EPCS or EPCQ configuration memory footprint in the schematic from day one - the configuration scheme must be designed into the board, not retrofitted; (3) neglecting the I/O bank voltage grouping - each of the 8 to 16 I/O banks has a separate VCCIO rail and only certain standards can be mixed within a bank; (4) ignoring the minimum and maximum supported configuration clock frequency for the chosen configuration mode; (5) forgetting the CRC or AES configuration check during board bring-up.
Compliance Information
RoHS, REACH, and lead-free status are not specified in the verified data. The N-suffixed variants (e.g. EP2S60F672C3N) are lead-free per Altera's standard suffix convention, but the non-N version of the EP2S60F672C3 may use SnPb solder balls. Designers should request a RoHS/REACH compliance certificate from the distributor before placing a production order.
