EP2SGX130GF40C3NES vs EP2SGX130GF40C4NES Comparison
Detailed side-by-side comparison of EP2SGX130GF40C3NES by Altera and EP2SGX130GF40C4NES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2SGX130GF40C3NES - Stratix II GX FPGA, 132K LE, 6.375Gbps | Altera
EP2SGX130GF40C3NES ObsoleteIntel
EP2SGX130GF40C4NES - 132K LE Stratix II GX FPGA, 6.375Gbps SERDES, 1508-FBGA | Intel
EP2SGX130GF40C4NES β Last Time BuySpecification Comparison
| Parameter | EP2SGX130GF40C3NES | EP2SGX130GF40C4NES |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $124.00 | $1,380.00 |
| Family | Stratix II GX | Stratix II GX |
| Logic Elements | 132540 | 132,540 |
| Logic Array Blocks (LABs) | 7047 | β |
| Maximum Internal Frequency | 778.82 MHz | β |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Transceiver Channels | 4 to 20 (per device family configuration) | Up to 20 (4 to 20, device-dependent) |
| Maximum Transceiver Data Rate | 6.375 Gbps | 6.375 Gbps |
| Transceiver Feature | Embedded SERDES with Clock/Data Recovery (CRU) | β |
| Memory Type | TriMatrix embedded memory (distributed RAM, block RAM, shift register) | β |
| Package | 1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch) | β |
| Operating Temperature Grade | Commercial Extended | β |
| Terminal Form | Ball (BGA) | β |
| Mounting Type | Surface Mount | Surface Mount (flip-chip BGA) |
| RoHS Status | Lead-free compliant (per package code MS-034AAU-1) | β |
| Series | EP2SGX130 | β |
| Logic Blocks / ALMs | β | Approximately 53,000 ALMs |
| User I/O Pins | β | 734 |
| Total Package Pins | β | 1508 (FC-FBGA ball grid) |
| Package Code | β | GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch) |
| Speed Grade | β | C4 (speed grade -4) |
| Internal Operating Frequency | β | Up to 717 MHz |
| Embedded Memory | β | Approximately 4.5 Mbits (TriMatrix) |
| PLL Blocks | β | 8 |
| DSP Blocks | β | Yes (variable, see datasheet) |
| Lead-Free / RoHS | β | Yes (LEAD FREE per datasheet family code) |
| MSL Level | β | Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level] |
| Operating Temperature | β | Commercial Extended (per N suffix) |
| JEDEC Standard Reference | β | MS-034AAU-1 |