EP610DC-10 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-10 | EP610DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $18.40 |
| Device Family | Altera Classic EPLD | β |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | β |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | β |
| Speed Grade | -10 | β |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Technology | CMOS, EPROM-based (UV-erasable) | β |
| Supply Voltage | 5 V (single supply) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | β |
| Logic Elements | 16 macrocells (programmable AND/OR array) | β |
| Configuration Memory | UV-erasable EPROM | β |
| Reprogrammable | Yes (UV erase window on package) | β |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | β | CPLD - Classic EPLD |
| Family | β | Altera Classic EP610 |
| Usable Gates | β | 300 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Frequency (fMAX) | β | 28.6 MHz |
| Pipelined Data Rate | β | up to 100 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Process Technology | β | CMOS |
| Program/erase Method | β | UV-erasable (windowed CERDIP) |
| Manufacturer | β | Originally Altera; today supplied via Rochester Electronics (authorized) |