EP610DC-10 vs EP610PC-15 Comparison

Detailed side-by-side comparison of EP610DC-10 by Intel and EP610PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610DC-10 EP610PC-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $7.95 $17.50
Device Family Altera Classic EPLD β€”
Macrocells 16 16
Maximum Pipelined Data Rate 100 MHz β€”
Pin-to-Pin Propagation Delay (tpd) 10 ns β€”
Speed Grade -10 β€”
Package 24-pin CDIP (Ceramic DIP, windowed) PDIP-24 (plastic DIP, 24-pin)
Mounting Type Through-Hole Through-Hole (DIP)
Technology CMOS, EPROM-based (UV-erasable) CMOS
Supply Voltage 5 V (single supply) β€”
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
I/O Pins [DATA_NEEDED: exact I/O count for CDIP-24 variant] β€”
Logic Elements 16 macrocells (programmable AND/OR array) β€”
Configuration Memory UV-erasable EPROM β€”
Reprogrammable Yes (UV erase window on package) β€”
RoHS Status [DATA_NEEDED: not stated in verified web data] [DATA_NEEDED: RoHS status]
Family β€” Classic EPLD
Device Type β€” EPLD (Erasable Programmable Logic Device)
Usable Gates β€” 300 gates
Logic Delay (tPD) β€” 15 ns (pin-to-pin, -15 speed grade)
Maximum Counter Frequency β€” 100 MHz (per family datasheet)
Pipelined Data Rate β€” Up to 100 MHz
Supply Voltage (VCC) β€” 5 V (single supply)
Architecture β€” PAL-type, sum-of-products AND/OR array
TTL Emulation β€” 100% TTL compatible
Pin Count β€” 24 pins
Development Tool β€” Altera MAX+PLUS II
Logic Test Circuitry β€” On-board for AC/DC verification

Datasheets & Resources

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