EP610DC-25 vs EP610DC-10 Comparison
Detailed side-by-side comparison of EP610DC-25 by Rochester Electronics and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610DC-25 | EP610DC-10 |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $7.95 |
| Family | Altera Classic EPLD | β |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | β |
| Maximum Propagation Delay (tPD) | 25 ns | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Number of I/O Pins | 22 | β |
| Number of Dedicated Inputs | 4 | β |
| Total Pin Count | 24 | β |
| Package | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through Hole | Through-Hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| Operating Temperature | 0 C to +70 C | 0C to +70C (commercial) |
| Technology | CMOS EPROM (UV-erasable) | CMOS, EPROM-based (UV-erasable) |
| Programming Method | JEDEC fuse-map / UV-erase | β |
| Speed Grade Suffix | -25 (25 ns tPD) | β |
| Device Family | β | Altera Classic EPLD |
| Maximum Pipelined Data Rate | β | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | β | 10 ns |
| Speed Grade | β | -10 |
| Supply Voltage | β | 5 V (single supply) |
| I/O Pins | β | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Logic Elements | β | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | β | UV-erasable EPROM |
| Reprogrammable | β | Yes (UV erase window on package) |
| RoHS Status | β | [DATA_NEEDED: not stated in verified web data] |