EP610DC-35 vs EP610DC-10 Comparison

Detailed side-by-side comparison of EP610DC-35 by Altera and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610DC-35 EP610DC-10
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.40 $7.95
Device Type CPLD - Classic EPLD β€”
Family Altera Classic EP610 β€”
Macrocells 16 16
Usable Gates 300 β€”
Propagation Delay (tPD) 35 ns β€”
Maximum Frequency (fMAX) 28.6 MHz β€”
Pipelined Data Rate up to 100 MHz β€”
Supply Voltage (VCC) 5 V β€”
Process Technology CMOS β€”
Program/erase Method UV-erasable (windowed CERDIP) β€”
Package 24-pin CDIP (windowed CERDIP) 0.300 inch 24-pin CDIP (Ceramic DIP, windowed)
Mounting Type Through-Hole (DIP) Through-Hole
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] 0C to +70C (commercial)
Manufacturer Originally Altera; today supplied via Rochester Electronics (authorized) β€”
RoHS Status [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] [DATA_NEEDED: not stated in verified web data]
Device Family β€” Altera Classic EPLD
Maximum Pipelined Data Rate β€” 100 MHz
Pin-to-Pin Propagation Delay (tpd) β€” 10 ns
Speed Grade β€” -10
Technology β€” CMOS, EPROM-based (UV-erasable)
Supply Voltage β€” 5 V (single supply)
I/O Pins β€” [DATA_NEEDED: exact I/O count for CDIP-24 variant]
Logic Elements β€” 16 macrocells (programmable AND/OR array)
Configuration Memory β€” UV-erasable EPROM
Reprogrammable β€” Yes (UV erase window on package)

Datasheets & Resources

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