EP610DC-35 vs EP610DC-25 Comparison

Detailed side-by-side comparison of EP610DC-35 by Altera and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Rochester Electronics
EP610DC-25

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 βœ“ Active

Specification Comparison

Parameter EP610DC-35 EP610DC-25
Brand Altera Rochester Electronics
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Active
Stock Status In Stock In Stock
Unit Price (USD) $18.40 $9.95
Device Type CPLD - Classic EPLD β€”
Family Altera Classic EP610 Altera Classic EPLD
Macrocells 16 16
Usable Gates 300 β€”
Propagation Delay (tPD) 35 ns β€”
Maximum Frequency (fMAX) 28.6 MHz β€”
Pipelined Data Rate up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V nominal)
Process Technology CMOS β€”
Program/erase Method UV-erasable (windowed CERDIP) β€”
Package 24-pin CDIP (windowed CERDIP) 0.300 inch 24-pin CDIP (Ceramic DIP, through-hole)
Mounting Type Through-Hole (DIP) Through Hole
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] 0 C to +70 C
Manufacturer Originally Altera; today supplied via Rochester Electronics (authorized) β€”
RoHS Status [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] β€”
Product Type β€” EPLD (Erasable Programmable Logic Device)
Equivalent Gates β€” 300
Maximum Propagation Delay (tPD) β€” 25 ns
Number of I/O Pins β€” 22
Number of Dedicated Inputs β€” 4
Total Pin Count β€” 24
Technology β€” CMOS EPROM (UV-erasable)
Programming Method β€” JEDEC fuse-map / UV-erase
Speed Grade Suffix β€” -25 (25 ns tPD)

Datasheets & Resources

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