EP610DC-35 vs EP610DC15 Comparison
Detailed side-by-side comparison of EP610DC-35 by Altera and EP610DC15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-35 | EP610DC15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.40 | $7.50 |
| Device Type | CPLD - Classic EPLD | β |
| Family | Altera Classic EP610 | EP610 Classic EPLD |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | β |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Process Technology | CMOS | β |
| Program/erase Method | UV-erasable (windowed CERDIP) | β |
| Package | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | 0C to +70C |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | β |
| RoHS Status | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | unknown |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Architecture | β | PAL-type |
| Maximum Clock Frequency (fMAX) | β | 71.4 MHz |
| Total Inputs | β | 20 |
| I/O Lines | β | 16 |
| Product Terms | β | 160 |
| Technology | β | CMOS |
| Reprogrammability | β | Yes (UV erasable via windowed package) |