EP610DC15 - 16-Macrocell Classic EPLD, 15ns tPD | Intel / Altera
MPN: EP610DC15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.95 | $995.00 |
| 500 | $8.75 | $4,375.00 |
| 1,000 | $7.5 | $7,500.00 |
EP610DC15 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits in the broader taxonomy of programmable logic devices (PLDs), which also include PALs, GALs, CPLDs, and FPGAs. EPLDs use EPROM or EEPROM cells to store the configuration, allowing them to be re-programmed and reused across design iterations. The Classic EPLD family preceded the modern MAX series and was historically used for glue logic, address decoding, state machines, and bus interfacing before FPGAs became cost-competitive.
Key features of the EP610DC15 include 71.4 MHz maximum clock frequency, CMOS technology with low power consumption, in-system erasability via the ceramic-windowed package, and JEDEC-standard pinout for socket compatibility with EP610DC-10/15/20/25/30/35 speed grades. The device supports both combinatorial and registered outputs with user-configurable macrocell flip-flops.
The EP610 architecture uses a global bus that distributes product terms to 16 macrocells, each containing a flip-flop and output enable control. This centralized interconnect provides predictable timing with fixed propagation delay, making it well-suited for asynchronous and synchronous logic replacement where deterministic behavior is required.
Typical applications include legacy industrial control replacement, address decoding for 8086/68000 microprocessor systems, state machine implementation, bus arbitration logic, and educational lab platforms. The wide supply tolerance and TTL-compatible I/O simplify integration with 5 V logic families.
When designing with this device, note that the EP610DC-15 is an NRND/EOL part. New designs should consider the Altera MAX II or MAX V CPLD families, which offer higher density, lower power, and modern packages. The CDIP-24 windowed package requires UV erasure for reprogramming.
Drop-in alternatives for EP610DC15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DC15 (same form factor and footprint) — differing in Package, Family, Technology, Operating Temperature, Propagation Delay (tPD).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610DC-10
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.95 / Unit
View Datasheet →EP610DC-20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$15.85 / Unit
View Datasheet →EP610DC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EP610DC-30
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.4 / Unit
View Datasheet →EP610DC-35
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$18.4 / Unit
View Datasheet →EP610DC15 Maximum Ratings & Electrical Characteristics
| Product Type | Classic EPLD (Erasable Programmable Logic Device) |
| Family | EP610 Classic EPLD |
| Macrocells | 16 |
| Architecture | PAL-type |
| Propagation Delay (tPD) | 15 ns |
| Maximum Clock Frequency (fMAX) | 71.4 MHz |
| Pipelined Data Rate | up to 100 MHz |
| Total Inputs | 20 |
| I/O Lines | 16 |
| Product Terms | 160 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Technology | CMOS |
| Operating Temperature | 0C to +70C |
| Package | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole |
| Reprogrammability | Yes (UV erasable via windowed package) |
| RoHS Status | unknown |
EP610DC15 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell 0) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell 1) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell 2) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell 3) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell 4) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell 5) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell 6) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell 7) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell 8) |
| Pin 10 | I/O — Bidirectional I/O pin (macrocell 9) |
| Pin 11 | I/O — Bidirectional I/O pin (macrocell 10) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Bidirectional I/O pin (macrocell 11) |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell 12) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell 13) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell 14) |
| Pin 17 | I/O — Bidirectional I/O pin (macrocell 15) |
| Pin 18 | INPUT — Dedicated input |
| Pin 19 | INPUT — Dedicated input |
| Pin 20 | INPUT — Dedicated input |
| Pin 21 | INPUT — Dedicated input / OE |
| Pin 22 | CLK — Dedicated clock input |
| Pin 23 | INPUT — Dedicated input |
| Pin 24 | VCC — +5V supply |
Typical Applications
EP610DC15 is suitable for 6 applications: Legacy Industrial Control Logic, Microprocessor Address Decoding, State Machine Implementation, Bus Arbitration and Interface Logic, Educational Laboratory and Training Platforms, Vintage Computer Restoration.
Legacy Industrial Control Logic
The EP610DC15's 15 ns propagation delay and 16 macrocells make it well suited for replacing legacy TTL glue logic in industrial control cabinets, particularly where 5 V supply and through-hole PCB assemblies must be retained. With 160 product terms and 20 inputs, it can implement combinational decoder and state-machine functions replacing 4-8 discrete TTL packages, reducing board area and assembly cost. The ceramic DIP package tolerates factory thermal environments within the 0C to +70C commercial range, and the CMOS technology provides noise immunity against motor-drive transients common on factory floors. Engineers maintaining legacy Allen-Bradley, Siemens, or GE control systems with EP610 sockets can source EP610DC15 as a direct replacement.
Recommended
Microprocessor Address Decoding
The EP610DC15 was widely used for address decoding in 8086, 68000, and Z80 microprocessor systems, where it generates chip-select signals for memory and peripheral ICs. Its 20 inputs are sufficient to decode 16-bit address buses plus control signals like MREQ, RD, and WR. The 15 ns tPD ensures the chip-select signals are valid within one clock cycle at 10 MHz 8086 systems, and the registered outputs provide glitch-free selects. With 16 macrocells, a single EP610DC15 can decode the entire memory map of an embedded system, replacing multiple 74LS138 or 74LS139 decoders. This application is documented in classic Altera application notes and remains the EP610's most common use case.
Recommended
State Machine Implementation
The EP610DC15 implements Moore and Mealy state machines with up to 16 states (one per macrocell flip-flop), supporting encoding schemes like binary, one-hot, and Gray code. Each macrocell's flip-flop can be clocked from the dedicated CLK pin or from a product-term-derived clock, enabling both synchronous and asynchronous state transitions. With 71.4 MHz fMAX, the EP610DC15 handles state machines clocked at speeds well beyond 8-bit microcontroller rates. Engineers use it to implement custom serial protocols, peripheral controllers, and sequencer logic where discrete flip-flop ICs would require multiple packages. The deterministic 15 ns tPD simplifies timing analysis compared to modern CPLD/FPGA architectures with variable routing delays.
Recommended
Bus Arbitration and Interface Logic
In multi-master bus systems, the EP610DC15 implements bus arbitration logic by monitoring REQUEST and GRANT signals and generating priority-encoded bus grants. With 16 macrocells and 20 inputs, it can arbitrate among 8 masters with full handshaking, replacing discrete 74LS148 priority encoders and 74LS279 latch circuits. The 15 ns tPD is well within the arbitration timing budget for ISA bus and similar 8-10 MHz parallel buses. The registered outputs provide clean, glitch-free grant signals. Industrial backplane designs and VMEbus cards in the late 1980s and 1990s frequently used the EP610DC15 for this purpose, and many legacy aerospace and defense systems still contain EP610-based arbitration logic requiring replacement parts.
Recommended
Educational Laboratory and Training Platforms
Universities and technical colleges historically used the EP610DC15 in digital logic design laboratories to teach programmable logic concepts, because the ceramic windowed package allows students to erase and reprogram devices multiple times during a single semester. The 16-macrocell complexity is appropriate for sophomore-level coursework - complex enough to implement meaningful designs like ALUs and simple CPUs, but small enough that students can hand-calculate timing budgets. The DIP-24 package fits standard IC sockets and breadboards, simplifying lab wiring. Modern curricula have largely transitioned to FPGAs, but the EP610DC15 remains in use at institutions maintaining legacy lab kits and in vintage computer restoration projects.
Recommended
Vintage Computer Restoration
The EP610DC15 appears in vintage computing platforms from the late 1980s including select Sun Microsystems workstations, DEC VAXstation peripherals, and custom industrial controllers, where it implements glue logic between the CPU, memory, and I/O subsystems. Restoration projects for these machines require sourcing original or compatible EPLDs because modern CPLDs use different packages and pinouts. The EP610DC15's windowed CDIP-24 package and JEDEC-standard fuse map allow it to be programmed with original device files from manufacturer archives. Hobbyists restoring SGI, Sun-3, and Apollo workstations rely on EP610DC15 stock for keeping these systems operational, with pricing reflecting the limited remaining inventory.
Recommended
Recommended Products Summary
Engineering reference data for EP610DC15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC-10 | EP610DC-20 | EP610DC-25 | EP610DC-30 | EP610DC-35 |
|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Package | 24-pin CDIP (windowed) | 24-pin CDIP (windowed) | 24-pin CDIP (windowed) | 24-pin CDIP (windowed) | 24-pin CDIP (windowed) | 24-pin CDIP (windowed) |
| Propagation Delay (tPD) | 15 ns | 10 ns | 20 ns | 25 ns | 30 ns | 35 ns |
| Maximum Clock Frequency | 71.4 MHz | 100 MHz | 62.5 MHz | 50 MHz | 42 MHz | 35.7 MHz |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Product Terms | 160 | 160 | 160 | 160 | 160 | 160 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Reprogrammability | Yes (UV erasable) | Yes (UV erasable) | Yes (UV erasable) | Yes (UV erasable) | Yes (UV erasable) | Yes (UV erasable) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Industry-standard CDIP-24 package with UV erasability (vs EP610PC15 (plastic DIP OTP))
- 15 ns speed grade balances speed and availability (vs EP610DC-10 (10 ns speed grade))
- JEDEC-standard fuse map for industry-standard programming tools (vs Generic PLD replacements)
Design Notes
Decouple VCC (pin 24) with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin, plus a 10 uF tantalum bulk capacitor at the board's power entry. The EP610DC15's CMOS inputs draw transient current during switching that can cause supply droop without adequate decoupling. For multi-EP610 designs, place one decoupling capacitor per device rather than sharing across the power rail.
The EP610DC15 is NRND/EOL - new designs should not select this part. For active replacements, use the Altera MAX II (EPM240T100C5N), MAX V (5M160ZE64C5N), or MAX 10 (10M02SCE144I7G) families which provide higher density, lower power, smaller surface-mount packages, and active Intel/Altera lifecycle support. Existing EP610 designs can be maintained by stocking EP610DC15 from authorized distributors before stock depletes.
Unused inputs must be tied to VCC or GND, not left floating. Floating CMOS inputs can oscillate, drawing excessive supply current and causing unpredictable macrocell behavior. For inputs not driven by an external signal, connect directly to VCC or GND via short traces to prevent noise pickup on the high-impedance CMOS gates. The dedicated input pins (18-23) and bidirectional I/O pins (1-11, 13-17) all require termination when unused.
The 24-pin CDIP package requires through-hole mounting with 2.54 mm (0.1 inch) pin pitch, suitable for standard IC sockets and breadboards. Keep trace lengths under 50 mm for clock signals to avoid timing skew. When programming the device in-circuit via JEDEC file, ensure the programmer socket or ISP header does not introduce capacitive loading exceeding 50 pF on any I/O pin, which can prevent successful programming or cause marginal readback.
Compliance Information
EP610DC15 is housed in a ceramic DIP package with lead-bearing solder finish (ceramic DIP packages predate RoHS exemptions for lead-based glass frits and pin plating). RoHS non-compliant status is typical for legacy ceramic-package ICs of this era. Not AEC-Q100 qualified - automotive applications should use MAX II/MAX V/MAX 10 with appropriate Q-grade variants.
