EP610DC-35 vs EP610DM-35 Comparison
Detailed side-by-side comparison of EP610DC-35 by Altera and EP610DM-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-35 | EP610DM-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.40 | $23.40 |
| Device Type | CPLD - Classic EPLD | β |
| Family | Altera Classic EP610 | β |
| Macrocells | 16 | β |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | β |
| Pipelined Data Rate | up to 100 MHz | β |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Process Technology | CMOS | β |
| Program/erase Method | UV-erasable (windowed CERDIP) | β |
| Package | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (CERDIP) with UV window |
| Mounting Type | Through-Hole (DIP) | β |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | β |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | Altera (Rochester Electronics authorized stock) |
| RoHS Status | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | Non-compliant (contains lead, hermetic CERDIP) |
| Part Family | β | Classic EPLD |
| Logic Family | β | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | β | 16 |
| Number of Gates | β | 300 |
| Pipelined Data Rate (fMAX) | β | 100 MHz |
| Temperature Grade (M) | β | Military -55Β°C to +125Β°C |
| I/O Pins | β | 24 dedicated I/O (input + bidirectional) |
| Programmability | β | UV-erasable, reprogrammable |
| Operating Temperature Range | β | -55Β°C to +125Β°C |
| MSL Level | β | [DATA_NEEDED: MSL rating] |