EP610DM-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
MPN: EP610DM-35 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $26.1 | $13,050.00 |
| 1,000 | $23.4 | $23,400.00 |
EP610DM-35 Overview
A Classic EPLD is a member of the early programmable logic device (PLD) family that preceded modern CPLDs and FPGAs. EPLDs provide sum-of-products logic, macrocell-based I/O, and non-volatile (UV-erasable) configuration in a small pin-count DIP, ideal for glue logic, address decoding, bus interfacing, and state-machine replacement in legacy industrial, telecom, and military systems. The EP610DM-35 sits within the broader taxonomy of programmable logic: PLD -> EPLD -> Classic EPLD -> CMOS PAL-type EPLD.
Key features include 24 dedicated input pins, 16 bidirectional I/O macrocells, a 35 ns pin-to-pin propagation delay (tPD), a 100 MHz pipelined fMAX, and a single 5 V supply. The 'D' suffix denotes the ceramic DIP package with a quartz window for UV erasure; the 'M' grade indicates military temperature range (-55C to +125C). The device is reprogrammable, JTAG-free, and uses Altera's MAX+plus II or classic Altera development tools for fitting.
Architecturally, the EP610DM-35 uses a programmable AND/OR array feeding 16 output macrocells with user-configurable flip-flops. Each macrocell can be set to combinatorial or registered output with dedicated feedback, allowing state machines, counters, and registered decoders. The Classic architecture is non-volatile, making the part an attractive choice for systems that must boot into a known logic state without external configuration memory.
Typical applications include legacy bus-interface glue logic in industrial controllers, address decoding in 80C86/80C88 and Motorola 68000 microprocessor systems, MIL-STD-1553 and ARINC-429 interface adapters, military/aerospace digital subsystems, and replacement of discrete TTL/CMOS glue in long-lifecycle equipment where modernization is impractical.
When designing with this device, ensure that the input rise/fall times meet the 5 V CMOS thresholds (typically <100 ns) to avoid spurious transitions, and budget sufficient tCO (clock-to-output) and tSU (setup-time) margins in synchronous paths. The 35 ns grade is appropriate for sub-30 MHz system clocks; for faster designs, select the EP610DI-25 (25 ns) or EP610DM-25 equivalent.
This page synthesizes distributor stock data, same-package EPLD alternatives, and design notes not found in the original Altera datasheet, supporting long-tail lifecycle maintenance for this mature Classic EPLD part.
Drop-in alternatives for EP610DM-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DM-35 (same form factor and footprint) — differing in Package, Operating Temperature, Family, I/O Pins, Propagation Delay (tPD).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610DI-35
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EP610DI-30
✅ Drop-In✓ In Stock
$23.5 / Unit
View Datasheet →EP610DI-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DC-35
✅ Drop-In✓ In Stock
$18.4 / Unit
View Datasheet →EP610DC-30
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP610DC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DM-35 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (Rochester Electronics authorized stock) |
| Part Family | Classic EPLD |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | 16 |
| Number of Gates | 300 |
| Propagation Delay (tPD) | 35 ns |
| Pipelined Data Rate (fMAX) | 100 MHz |
| Supply Voltage (VCC) | 5 V (single supply) |
| Package | 24-pin CDIP (CERDIP) with UV window |
| Temperature Grade (M) | Military -55°C to +125°C |
| I/O Pins | 24 dedicated I/O (input + bidirectional) |
| Programmability | UV-erasable, reprogrammable |
| Operating Temperature Range | -55°C to +125°C |
| RoHS Status | Non-compliant (contains lead, hermetic CERDIP) |
EP610DM-35 Pin Configuration
| Pin 1 | I/O — Bidirectional macrocell I/O pin |
| Pin 2 | I/O — Bidirectional macrocell I/O pin |
| Pin 3 | I/O — Bidirectional macrocell I/O pin |
| Pin 4 | I/O — Bidirectional macrocell I/O pin |
| Pin 5 | I/O — Bidirectional macrocell I/O pin |
| Pin 6 | I/O — Bidirectional macrocell I/O pin |
| Pin 7 | I/O — Bidirectional macrocell I/O pin |
| Pin 8 | I/O — Bidirectional macrocell I/O pin |
| Pin 9 | I/O — Bidirectional macrocell I/O pin |
| Pin 10 | I/O — Bidirectional macrocell I/O pin |
| Pin 11 | I/O — Bidirectional macrocell I/O pin |
| Pin 12 | GND — Ground (per datasheet pinout convention) |
| Pin 13 | INPUT — Dedicated input pin |
| Pin 14 | INPUT — Dedicated input pin |
| Pin 15 | INPUT — Dedicated input pin |
| Pin 16 | INPUT — Dedicated input pin |
| Pin 17 | INPUT — Dedicated input pin |
| Pin 18 | INPUT — Dedicated input pin |
| Pin 19 | INPUT — Dedicated input pin |
| Pin 20 | INPUT — Dedicated input pin |
| Pin 21 | INPUT — Dedicated input pin |
| Pin 22 | INPUT — Dedicated input pin |
| Pin 23 | INPUT — Dedicated input pin |
| Pin 24 | VCC — +5 V supply (per datasheet pinout convention) |
Typical Applications
EP610DM-35 is suitable for 6 applications: Legacy 80C86/80C88 Bus Address Decoding, Motorola 68000 Glue Logic and Interrupt Controller, MIL-STD-1553 and ARINC-429 Interface Adapters, Industrial PLC Discrete I/O Expansion, Legacy Telecom Backplane Glue Logic, Replacement of Discrete 74LS/74HC TTL Glue Logic.
Legacy 80C86/80C88 Bus Address Decoding
The EP610DM-35's 16 macrocells and 24 dedicated inputs suit 80C86/80C88 microprocessor address-decoding tasks perfectly, replacing 4-6 discrete 74LS/74HC TTL packages per EPLD. With 35 ns tPD the device comfortably meets 8 MHz and most 10 MHz 80C86 timing budgets while drawing negligible standby current. Engineers typically use the device to decode chip-selects, generate wait-state logic, and arbitrate shared bus resources across ROM, RAM, and peripheral banks, reducing board area and BOM cost in industrial controllers still based on legacy x86 architectures.
Recommended
Motorola 68000 Glue Logic and Interrupt Controller
In Motorola 68000-based VMEbus and industrial-automation systems, the EP610DM-35 functions as compact glue logic that consolidates address decoding, DTACK generation, bus-error handling, and interrupt prioritization into a single non-volatile part. The Classic EPLD's registered macrocells handle synchronous 68000 bus cycles, while the combinatorial paths support asynchronous interrupt acknowledge sequences. With 35 ns tPD, the part is adequate for 8 MHz 68000 systems and a drop-in replacement choice for legacy aerospace and defense cards where redesign is impractical.
Recommended
MIL-STD-1553 and ARINC-429 Interface Adapters
Avionics and military databus systems use the EP610DM-35 to build Manchester-II encoders/decoders, parity generators, and protocol-state machines in a small footprint. The military temperature grade (-55C to +125C) and MIL-STD-883 processing variants make the device suitable for line-replaceable units (LRUs) on rotary- and fixed-wing platforms. The 16-macrocell density is appropriate for sub-functions of MIL-STD-1553B remote terminals, while its non-volatile UV-erasable configuration eliminates the boot-time complexity of SRAM-based FPGAs.
Recommended
Industrial PLC Discrete I/O Expansion
Programmable Logic Controllers (PLCs) and industrial I/O expansion cards use the EP610DM-35 to debounce, multiplex, and latch 24-V industrial inputs into logic-level signals for the host CPU. The 24 input pins accept direct connection from opto-isolated inputs, and the registered macrocells synchronize events to the PLC scan cycle. The military temperature rating provides headroom for harsh factory-floor environments, while the UV-erasable reprogrammability allows field updates to debounce and timing logic without firmware rework.
Recommended
Legacy Telecom Backplane Glue Logic
Telecom backplanes for legacy T1/E1, ISDN, and POTS equipment use the EP610DM-35 to perform bus arbitration, time-slot switching, and alarm-logic functions in CO (central-office) line cards. The Classic EPLD's 5 V CMOS interface matches the supply rails of vintage DSP and framer ASICs, and its 35 ns tPD keeps up with T1 (1.544 MHz) and E1 (2.048 MHz) time-slot rates with substantial margin. Field-proven reliability and the part's long-term availability through Rochester Electronics support multi-decade telecom deployment.
Recommended
Replacement of Discrete 74LS/74HC TTL Glue Logic
Engineers use the EP610DM-35 to replace 4-8 discrete 74LS/74HC gates, latches, and multiplexers with a single non-volatile, reprogrammable device. This consolidation reduces PCB area, improves noise immunity (single device replaces multiple SSI/MSI packages), and simplifies BOM. The 35 ns tPD easily replaces 74LS-series logic (10 ns typical 74LS04 vs 35 ns EPLD macrocell path is comparable for most non-critical paths), and the UV-erasable window allows in-lab design iterations.
Recommended
Recommended Products Summary
Engineering reference data for EP610DM-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DI-35 | EP610DI-30 | EP610DI-25 | EP610DC-35 | EP610DC-30 |
|---|---|---|---|---|---|---|
| Package | CDIP-24 (windowed CERDIP) | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same |
| Brand | Altera (Rochester authorized stock) | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tPD) | 35 ns | 35 ns | 30 ns | 25 ns | 35 ns | 30 ns |
| Pipelined fMAX | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Temperature Grade | Military -55C to +125C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +70C | Commercial 0C to +70C |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete (Rochester stock only) | Obsolete (Rochester stock only) | Obsolete (Rochester stock only) | Obsolete (Rochester stock only) | Obsolete (Rochester stock only) | Obsolete (Rochester stock only) |
Key Differentiators
- Military temperature grade qualification (vs EP610DC-35)
- Slower speed grade with established military baseline (vs EP610DM-25 / EP610DM-30)
- Authorized continuing-source availability (vs EP610DM883B (full MIL-STD-883B screening))
Design Notes
Estimated: at 5 V supply and 24 I/O pins each switching 10 pF load at 1 MHz, total dynamic power is approximately P = C * V^2 * f * N = 10 pF * 25 * 1 MHz * 24 = 6 mW. Static current is typically <50 mA for the EP610DM-35 family per Altera datasheet. The CDIP-24 ceramic package has excellent thermal performance and requires no heatsink even at full military temperature operation.
Place a 0.1 uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 24) and a bulk 10 uF tantalum or electrolytic capacitor on the same supply trace. For multi-EPLD boards, add a 10 uF tantalum per device. Keep input traces short and avoid routing inputs near high-frequency switching signals to prevent false triggering of the EP610's TTL/CMOS-compatible input buffers.
The EP610DM-35 requires a UV erasure step before reprogramming - budget 30-60 minutes of UV exposure (wavelength 2537 Angstrom, intensity 12,000 uW/cm^2) to fully erase the device. Do not exceed 7 V absolute maximum on any I/O pin; the EP610 is a 5 V part with limited 5 V tolerance on input overvoltage. Confirm the temperature grade matches the deployment environment - the 'M' suffix is mandatory for -55C operation, otherwise use 'I' or 'C' grade.
Compliance Information
CDIP-24 ceramic DIP package with UV window contains lead, exceeding RoHS thresholds. Part is not AEC-Q100 qualified (not an automotive-grade part). REACH and conflict-mineral status not explicitly stated by Rochester Electronics for this legacy part.
