EP610DC35 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DC35 by Altera and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC35 | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.20 | $18.40 |
| Family | Classic EPLD | Altera Classic EP610 |
| Logic Elements | 16 macrocells | β |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency | 28.6 MHz | β |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage | 5 V | β |
| Package | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Pin Count | 24 | β |
| Technology | UV-erasable CMOS EPROM | β |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | β |
| Device Type | β | CPLD - Classic EPLD |
| Macrocells | β | 16 |
| Maximum Frequency (fMAX) | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Process Technology | β | CMOS |
| Program/erase Method | β | UV-erasable (windowed CERDIP) |
| Manufacturer | β | Originally Altera; today supplied via Rochester Electronics (authorized) |