EP610DC35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
MPN: EP610DC35 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $30.91 | $30.91 |
| 10 | $28.5 | $285.00 |
| 100 | $24.8 | $2,480.00 |
| 500 | $21.5 | $10,750.00 |
| 1,000 | $19.2 | $19,200.00 |
EP610DC35 Overview
Classic EPLDs (Erasable Programmable Logic Devices) are ultraviolet-erasable, CMOS-based programmable logic devices that pre-date modern CPLDs and FPGAs. They belong to the broader category of programmable logic devices (PLDs), which also include SPLDs, CPLDs, and FPGAs. EP610-series devices are organized as a single AND/OR logic block feeding a fixed-output macrocell array, providing predictable timing suitable for address decoding, bus interfacing, and glue-logic replacement in 5V systems.
Key features include 16 macrocells, 300 gates of usable logic, a maximum propagation delay of 35ns (tPD), and a 5V single-supply operation with 5V-tolerant I/O. The EP610DC35 is windowed (ceramic DIP with quartz erase window) and is one of the speed grades in the EP610 family, distinguished from -10, -15, -20, -25, and -30 grades by its 35ns timing. The device supports both combinational and registered logic with pin-feedback architecture and is in-system programmable via Altera's classic programming algorithm.
Architecturally, the EP610 uses Altera's Classic EPLD macrocell with sum-of-products logic feeding programmable flip-flops, plus a global clock network and JTAG-free programming interface. The 5V CMOS EPROM technology yields high noise immunity and latch-up resistance, making it well suited to industrial control boards, avionics retrofits, and 5V legacy embedded platforms where modern 3.3V/2.5V PLDs are not pin-compatible replacements.
Typical applications include 5V bus interface glue logic, address decoding for M68k and x86 embedded systems, state-machine controllers, peripheral chip replacement, and military/aerospace systems requiring 5V tolerance and high reliability. The CDIP-24 ceramic package offers extended temperature performance and is preferred over plastic DIPs in aerospace and defense systems.
When designing with the EP610DC35, note that it is programmed with an Altera legacy programmer (e.g., PLDLMax or compatible) and cannot be re-programmed in-system via JTAG. Designs should also budget the 35ns tPD carefully when interfacing to high-speed buses; for faster speeds the EP610DC-25 or EP610DC-20 grades should be considered.
Drop-in alternatives for EP610DC35 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DC35 (same form factor and footprint) β differing in Family, Package, Propagation Delay (tPD), Technology, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610DC30
β Drop-Inπ Reference alternative (not in catalog)
EP610DC25
β Drop-Inπ Reference alternative (not in catalog)
EP610DC20
β Drop-Inπ Reference alternative (not in catalog)
EP610DC15
β Drop-Inβ In Stock
$7.5 / Unit
View Datasheet βEP610DC10
β Drop-Inπ Reference alternative (not in catalog)
EP610DC-35
β Drop-Inβ In Stock
$18.4 / Unit
View Datasheet βEP610DC35 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Logic Elements | 16 macrocells |
| Usable Gates | 300 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Frequency | 28.6 MHz |
| Pipelined Data Rate | up to 100 MHz |
| Supply Voltage | 5 V |
| Package | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| Mounting Type | Through-Hole |
| Pin Count | 24 |
| Technology | UV-erasable CMOS EPROM |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) |
EP610DC35 Pin Configuration
| Pin 1 | I/O β Macrocell I/O pin (function programmable) |
| Pin 2 | I/O β Macrocell I/O pin (function programmable) |
| Pin 3 | I/O β Macrocell I/O pin (function programmable) |
| Pin 4 | I/O β Macrocell I/O pin (function programmable) |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β Macrocell I/O pin (function programmable) |
| Pin 7 | I/O β Macrocell I/O pin (function programmable) |
| Pin 8 | I/O β Macrocell I/O pin (function programmable) |
| Pin 9 | I/O β Macrocell I/O pin (function programmable) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β Macrocell I/O pin (function programmable) |
| Pin 12 | I/O β Macrocell I/O pin (function programmable) |
| Pin 13 | I/O β Macrocell I/O pin (function programmable) |
| Pin 14 | I/O β Macrocell I/O pin (function programmable) |
| Pin 15 | GND β Ground |
| Pin 16 | I/O β Macrocell I/O pin (function programmable) |
| Pin 17 | I/O β Macrocell I/O pin (function programmable) |
| Pin 18 | I/O β Macrocell I/O pin (function programmable) |
| Pin 19 | I/O β Macrocell I/O pin (function programmable) |
| Pin 20 | VCC β +5V supply |
| Pin 21 | I/O β Macrocell I/O pin (function programmable) |
| Pin 22 | I/O β Macrocell I/O pin (function programmable) |
| Pin 23 | I/O β Macrocell I/O pin (function programmable) |
| Pin 24 | VCC β +5V supply |
Typical Applications
EP610DC35 is suitable for 6 applications: 5V Industrial Glue Logic Replacement, M68k / x86 Embedded Address Decoding, Aerospace / Defense Legacy Avionics, Peripheral Chip Replacement / Consolidation, State Machine Controllers, Test & Measurement Instrument Logic.
5V Industrial Glue Logic Replacement
The EP610DC35 replaces discrete 74LS/74HC glue logic in 5V industrial control boards where 16 macrocells of deterministic logic are sufficient. Its 35 ns tPD easily meets typical control-loop update rates below 1 MHz, and the 5V CMOS EPROM technology provides high noise immunity on long cable harnesses. According to Altera's Classic EPLD datasheet, a single EP610DC35 can replace 4-6 small-scale integration TTL packages, reducing board area and BOM cost in legacy PLC and motor-controller retrofits.
Recommended
M68k / x86 Embedded Address Decoding
The EP610DC35 is widely used for address decoding in 5V M68k and x86 embedded systems where multiple peripheral chips must be mapped into a single memory or I/O window. With 16 macrocells and 35 ns tPD, it fits between a 10-15 MHz CPU bus and slow peripherals like UARTs, timers, and SRAM, without introducing wait states. The 5V-tolerant I/O and ceramic DIP package make it a long-term reliable decoder in industrial single-board computers manufactured through the 1990s and 2000s.
Recommended
Aerospace / Defense Legacy Avionics
The EP610DC35's CDIP-24 ceramic package and high-reliability screening make it suitable for aerospace and defense avionics retrofits where plastic packages are prohibited by specification. Operating from a single 5V supply with UV-erasable EPROM technology, it provides non-volatile logic that survives power cycles and radiation events common in avionics environments. According to Rochester Electronics' longevity program, EP610-family parts continue to be supported for defense logistics sustainment as of 2026-09-10.
Recommended
Peripheral Chip Replacement / Consolidation
Designers use the EP610DC35 to consolidate multiple 74-series decoder, multiplexer, and latch functions into a single programmable device, reducing PCB area and improving reliability. With 16 macrocells and 300 usable gates, the EP610DC35 can absorb 4-6 SSI/MSI packages in typical address-decoding or bus-control applications. The 35 ns tPD grade is sufficient for buses operating up to ~14 MHz, which covers most ISA, PC/104, and parallel peripheral interfaces still found in industrial equipment.
Recommended
State Machine Controllers
The EP610DC35 implements Moore and Mealy state machines for sequential control logic in industrial automation, replacing discrete flip-flop and gate arrays. With 16 macrocells providing registered outputs and combinational feedback, it can encode state machines with up to ~16 states using one-hot or binary encoding. The 5V CMOS EPROM technology ensures deterministic timing and high noise immunity required for factory-floor motor and process control, as documented in the manufacturer datasheet.
Recommended
Test & Measurement Instrument Logic
The EP610DC35 provides timing, sequencing, and signal-routing logic in legacy bench-top test and measurement instruments such as oscilloscopes, signal generators, and protocol analyzers. Its 35 ns tPD comfortably handles front-panel switch debouncing, range-selection decoding, and display multiplexing for instruments with kHz-to-low-MHz update rates. The ceramic DIP package also tolerates the wide operating-temperature environments found in laboratory and field-test equipment.
Recommended
Recommended Products Summary
Engineering reference data for EP610DC35 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC30 | EP610DC25 | EP610DC20 | EP610DC15 | EP610DC10 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CDIP-24 | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same |
| Propagation Delay (tPD) | 35 ns | 30 ns | 25 ns | 20 ns | 15 ns | 10 ns |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Maximum Frequency | 28.6 MHz | 33.3 MHz | 40 MHz | 50 MHz | 66.7 MHz | 100 MHz |
| Technology | UV-EPROM CMOS | UV-EPROM CMOS | UV-EPROM CMOS | UV-EPROM CMOS | UV-EPROM CMOS | UV-EPROM CMOS |
| Programming Method | Altera legacy programmer | Altera legacy programmer | Altera legacy programmer | Altera legacy programmer | Altera legacy programmer | Altera legacy programmer |
Key Differentiators
- Slowest speed grade in the EP610 family - lowest cost option for non-timing-critical designs (vs EP610DC30)
- Higher logic density than 22V10-style PALs while remaining pin-compatible with CDIP-24 footprint (vs PALCE22V10H-15PC)
- Ceramic DIP package qualifies for high-reliability and defense applications (vs MAX II EPM240T100C5N)
Design Notes
The EP610DC35 is NOT in-system programmable and has no JTAG interface. Programming requires an Altera legacy programmer (PLDLMax or compatible) and is performed before PCB mounting. Designs targeting prototype iteration should plan for external programming sockets (e.g., DIP-24 ZIF) or consider MAX II CPLDs with JTAG-ISP. Erasure requires 20+ minutes of UV exposure through the quartz window.
The CDIP-24 ceramic package of the EP610DC35 offers superior thermal performance compared to plastic DIP, but still requires attention in high-density legacy designs. Estimated: at 5V VCC and CMOS switching activity around 10 MHz, quiescent current is typically 100-200 mA, dissipating 0.5-1W. Mount the device with adequate copper pour or socketed in air flow to maintain junction temperature below 125Β°C. The quartz erase window also degrades at sustained high temperatures; conformal coating can protect against handling damage.
Place decoupling capacitors (0.1 Β΅F ceramic in parallel with 10 Β΅F tantalum) directly at each VCC pin (pins 20 and 24) of the EP610DC35 with traces shorter than 5 mm. The GND pins (5, 10, 15) should connect to a low-impedance ground plane rather than individual traces. According to Altera's Classic EPLD design guidelines, keep TTL/CMOS input rise/fall times below 200 ns and use series termination on long signal traces to limit undershoot below -0.5V.
Do not confuse the EP610DC35 (35 ns, ceramic DIP, 24 pins) with the EP910 series or with plastic PDIP variants. Also note that the -35 speed grade is the slowest in the EP610 family; the datasheet's pipelined data rate of 100 MHz applies only to internal register-to-register paths with fMAX=28.6 MHz at the I/O pins. Always compute worst-case timing using the datasheet tPD, tCO, and tSU parameters against your target bus frequency.
Compliance Information
EP610DC35 is an obsolete Altera part manufactured before 2000. RoHS, REACH, and lead-free status were not specified in the verified web data or manufacturer datasheet; values set to 'unknown'. AEC-Q100 not applicable to PLDs of this vintage.
