EP610DC35 vs EP610DC15 Comparison
Detailed side-by-side comparison of EP610DC35 by Altera and EP610DC15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC35 | EP610DC15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.20 | $7.50 |
| Family | Classic EPLD | EP610 Classic EPLD |
| Logic Elements | 16 macrocells | β |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Frequency | 28.6 MHz | β |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage | 5 V | β |
| Package | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole | Through-Hole |
| Pin Count | 24 | β |
| Technology | UV-erasable CMOS EPROM | CMOS |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 16 |
| Architecture | β | PAL-type |
| Maximum Clock Frequency (fMAX) | β | 71.4 MHz |
| Total Inputs | β | 20 |
| I/O Lines | β | 16 |
| Product Terms | β | 160 |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Reprogrammability | β | Yes (UV erasable via windowed package) |