EP610IPC-10 vs EP610JI-30 Comparison
Detailed side-by-side comparison of EP610IPC-10 by Altera and EP610JI-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IPC-10 | EP610JI-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $9.40 |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP610) |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Programmable Gates | 300 usable gates | β |
| Macrocells | 16 | 16 |
| Maximum Operating Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | β |
| Product Terms | 160 total | 160 |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | 16 |
| Total Input Pins | 20 | β |
| Supply Voltage | 5 V | 5 V (single supply) |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | β |
| Technology | CMOS EPROM (UV-erasable / OTP) | β |
| Package | 24-pin PDIP (Plastic DIP) | CQCC28 (windowed ceramic JLCC, J-bend) |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial, per EP610 family suffix convention) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | β |
| TTL Emulation | 100% TTL compatible | β |
| Propagation Delay (tpd) | β | 30 ns (max) |
| Pipelined Data Rate | β | Up to 100 MHz |
| External Clocks | β | 2 |
| Process Technology | β | CMOS |
| Package Code | β | JLCC-28 / CQCC28 |
| Erasure Method | β | Ultraviolet (UV) via top window |
| Programming | β | Altera Logic Programmer compatible |
| Mounting Type | β | Surface Mount (JLCC) |
| RoHS Status | β | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |