EP610JI-30 vs EP610IPC-10 Comparison
Detailed side-by-side comparison of EP610JI-30 by Altera and EP610IPC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610JI-30 | EP610IPC-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.40 | $16.40 |
| Family | Altera Classic EPLD (EP610) | Altera Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Product Terms | 160 | 160 total |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | 16 |
| External Clocks | 2 | β |
| Supply Voltage | 5 V (single supply) | 5 V |
| Process Technology | CMOS | β |
| Package | CQCC28 (windowed ceramic JLCC, J-bend) | 24-pin PDIP (Plastic DIP) |
| Package Code | JLCC-28 / CQCC28 | β |
| Erasure Method | Ultraviolet (UV) via top window | β |
| Programming | Altera Logic Programmer compatible | β |
| Operating Temperature | -40C to +85C (industrial, per EP610 family suffix convention) | -40C to +85C (industrial) |
| Mounting Type | Surface Mount (JLCC) | β |
| RoHS Status | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | β |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Programmable Gates | β | 300 usable gates |
| Maximum Operating Frequency | β | 100 MHz |
| Propagation Delay (tPD) | β | 15 ns (commerical -10 grade) |
| Total Input Pins | β | 20 |
| Architecture | β | Turbo-only AND-OR-NOT, PAL-type |
| Technology | β | CMOS EPROM (UV-erasable / OTP) |
| Programming Method | β | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | β | 100% TTL compatible |