EP610LC-35 vs EP610JI-30 Comparison
Detailed side-by-side comparison of EP610LC-35 by Altera and EP610JI-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-35 | EP610JI-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.40 |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP610) |
| Device Series | EP610 | β |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | β |
| Propagation Delay (tpd) | 37 ns | 30 ns (max) |
| Supply Voltage (Vcc) | 5 V | β |
| Technology | CMOS EEPROM (one-time-programmable plastic) | β |
| Package | 28-pin PLCC (J-lead) | CQCC28 (windowed ceramic JLCC, J-bend) |
| Operating Temperature | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | -40C to +85C (industrial, per EP610 family suffix convention) |
| Speed Grade | -35 (slowest EP610) | β |
| Mounting Type | Surface Mount | Surface Mount (JLCC) |
| Programmable Pins | 24 input / 16 output (shared macrocells) | β |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead_free] | [DATA_NEEDED: lead-free status] |
| MSL Level | [DATA_NEEDED: msl_level] | β |
| Programming Tool | MAX+PLUS II development system | β |
| Device Type | β | UV Erasable Programmable Logic Device (EPLD) |
| Pipelined Data Rate | β | Up to 100 MHz |
| Product Terms | β | 160 |
| Dedicated Inputs | β | 4 |
| I/O Pins | β | 16 |
| External Clocks | β | 2 |
| Supply Voltage | β | 5 V (single supply) |
| Process Technology | β | CMOS |
| Package Code | β | JLCC-28 / CQCC28 |
| Erasure Method | β | Ultraviolet (UV) via top window |
| Programming | β | Altera Logic Programmer compatible |