EP610LI-25 vs EP610PC-25T Comparison
Detailed side-by-side comparison of EP610LI-25 by Rochester Electronics and EP610PC-25T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610LI-25 - 16-Macrocell Classic EPLD, 25ns, CMOS | Altera / Rochester Electronics
EP610LI-25 β ActiveIntel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T β Last Time BuySpecification Comparison
| Parameter | EP610LI-25 | EP610PC-25T |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.25 | $28.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EP610 | β |
| Macrocells | 16 | β |
| Usable Gates | 300 | β |
| Maximum Propagation Delay (tPD) | 25 ns | β |
| Pipelined Data Rate (fMAX) | 100 MHz | β |
| Speed Grade | 25 (25 ns tPD) | β |
| Power Variant | L (low-power CMOS) | β |
| Temperature Grade | I (industrial) | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 16 | β |
| Technology | CMOS, UV-erasable (windowed) | β |
| Package | Ceramic DIP-24 (windowed, Altera 'I' designation) | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) |
| Mounting Type | Through-hole | Through-hole |
| Programming Method | Altera MAX+PLUS II / Classic compiler + compatible programmer | OTP (one-time programmable) via Altera programming hardware |
| RoHS Status | Unknown - ceramic DIP legacy package | [DATA_NEEDED: RoHS status] |
| Manufacturer / Source | Altera (original), Rochester Electronics (authorized continuing supplier) | β |
| Manufacturer | β | Intel (formerly Altera) |
| Distributor / Stocking Source | β | Rochester Electronics, LLC |
| Device Family | β | Altera Classic EPLD - EP610 |
| Device Type | β | Erasable Programmable Logic Device (EPLD, OTP for plastic package) |
| Logic Capacity | β | 300 usable gates |
| Macro Cells | β | 16 |
| Registers | β | 16 |
| User I/Os | β | 16 |
| Propagation Delay (tPD) | β | 25 ns (speed grade 25) |
| Maximum Toggle Frequency | β | [DATA_NEEDED: max fmax] |
| Pipelined Data Rate | β | up to 100 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Process Technology | β | ECMOS (CMOS, EPROM-based) |
| Pinout Compatibility | β | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) |
| Operating Temperature | β | 0 Β°C to +70 Β°C (commercial) |
| Shipping Form (T suffix) | β | Tube |