EP610LI-25 - 16-Macrocell Classic EPLD, 25ns, CMOS | Altera / Rochester Electronics
MPN: EP610LI-25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.63 | $28.63 |
| 10 | $25.5 | $255.00 |
| 100 | $22 | $2,200.00 |
| 500 | $19.5 | $9,750.00 |
| 1,000 | $17.25 | $17,250.00 |
EP610LI-25 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC (PLD) that combines multiple PAL-like macrocells on a single CMOS die, erasable via ultraviolet light through a quartz window on windowed packages. Classic EPLDs occupy the architectural middle ground between simple PALs/GALs and modern high-density FPGAs or CPLDs: they offer deterministic combinatorial and registered logic, predictable pin-to-pin timing, and simple development flows based on Altera's legacy MAX+PLUS II / Classic compiler toolchain. In a system hierarchy, EPLDs sit under CPLDs and FPGAs but above discrete 74-series glue logic for designs needing a few hundred gates of custom decode, state-machine, or bus-interface logic.
Key features include 16 macrocells, 300 usable gates, 25 ns tPD, 100 MHz pipelined fMAX, 4 dedicated inputs plus 16 I/O pins, and programmable output macrocell polarity. The device offers three-state output control on every I/O pin, a synchronous preset/reset structure shared across the macrocell array, and low CMOS standby current typical of the 'L' power variant. JTAG/boundary-scan test is not present on this Classic part - test access is via the standard functional pins and the dedicated programming algorithm.
From an architectural standpoint, the EP610 is a sum-of-products AND-OR array feeding a global interconnect that drives 16 output macrocells. Each macrocell contains a flip-flop, output polarity bit, and three-state buffer that can be individually enabled. This structure delivers predictable, deterministic timing that does not require place-and-route iteration, making EP610 designs reproducible across production lots.
Typical applications include legacy glue-logic replacement on industrial and military backplanes, address decoding for 8- and 16-bit microprocessor systems (8086, 68000, Z80), bus arbitration and interrupt controllers, state-machine controllers, and small peripheral interfaces where modern CPLD/FPGA density is unnecessary. The 'I' temperature grade and ceramic package also make it suitable for extended-temperature and Mil-spec system designs still in active production.
When designing with EP610LI-25, use Altera MAX+PLUS II or the Classic compiler with a supported programmer, and respect the 25 ns tPD budget when cascading logic across multiple macrocells. For new designs, prefer the EP610LI-20 or EP610LI-15 speed grades if timing margin is tight; the EP610 family shares pinout across all speed grades, simplifying speed up/down swap on existing boards.
This page synthesizes distributor pricing from Rochester Electronics and authorized partners, lists same-family drop-in pin-compatible alternatives from the EP610 family, and surfaces practical programming and design notes not consolidated in the original Altera datasheet.
Drop-in alternatives for EP610LI-25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610LI-25 (same form factor and footprint) — differing in Package, Operating Temperature, Programming Method, Propagation Delay (tPD), Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610LI-20
✅ Drop-In✓ In Stock
$18.2 / Unit
View Datasheet →EP610LI-15
✅ Drop-In✓ In Stock
$48.5 / Unit
View Datasheet →EP610ILI-25
✅ Drop-In📋 Reference alternative (not in catalog)
EP610DC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DC-30
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP610DC-20
✅ Drop-In✓ In Stock
$15.85 / Unit
View Datasheet →EP610LI-25 Maximum Ratings & Electrical Characteristics
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EP610 |
| Macrocells | 16 |
| Usable Gates | 300 |
| Maximum Propagation Delay (tPD) | 25 ns |
| Pipelined Data Rate (fMAX) | 100 MHz |
| Speed Grade | 25 (25 ns tPD) |
| Power Variant | L (low-power CMOS) |
| Temperature Grade | I (industrial) |
| Dedicated Inputs | 4 |
| I/O Pins | 16 |
| Technology | CMOS, UV-erasable (windowed) |
| Package | Ceramic DIP-24 (windowed, Altera 'I' designation) |
| Mounting Type | Through-hole |
| Programming Method | Altera MAX+PLUS II / Classic compiler + compatible programmer |
| RoHS Status | Unknown - ceramic DIP legacy package |
| Manufacturer / Source | Altera (original), Rochester Electronics (authorized continuing supplier) |
EP610LI-25 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 9 | INPUT — Dedicated input pin |
| Pin 10 | GND — Ground |
| Pin 11 | INPUT — Dedicated input pin |
| Pin 12 | INPUT — Dedicated input pin |
| Pin 13 | INPUT — Dedicated input pin |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 17 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 18 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 19 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 20 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 21 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 22 | VCC — +5V supply |
| Pin 23 | NC — Not connected (per EP610 family datasheet convention) |
| Pin 24 | NC — Not connected (per EP610 family datasheet convention) |
Typical Applications
EP610LI-25 is suitable for 6 applications: Legacy 8/16-bit Microprocessor Address Decoding, Bus Arbitration and Interrupt Controller Glue Logic, State Machine and Protocol Converter Controllers, Military / Aerospace Sustaining Engineering, Industrial PLC and Process Control Backplanes, Test & Measurement Legacy Instrument Repair.
Legacy 8/16-bit Microprocessor Address Decoding
The EP610LI-25's 16 macrocells and deterministic 25 ns tPD fit naturally between 8086/68000/Z80 address buses and peripheral chip-select lines where modern CPLDs would be overkill. With 300 usable gates, the part can decode the full 64K address space of an 8-bit CPU or the lower 16-bit address space of a 16-bit CPU with room left over for wait-state and interrupt-acknowledge glue logic. Designers typically use EP610LI-25 to consolidate three or four 74LS138 / 74LS139 decoder chips into a single socketed ceramic DIP, simplifying PCB layout and reducing decode-skew that plagues cascaded discrete decoders. The low-power 'L' CMOS variant also keeps standby current negligible, important for battery-backed industrial controllers. Programmability via UV erasure means field firmware revisions do not require board respins.
Recommended
Bus Arbitration and Interrupt Controller Glue Logic
Multi-master VME, Multibus, or industrial backplane designs need deterministic bus arbitration and prioritized interrupt handling - exactly the use case where the EP610LI-25 excels. The 16 macrocells can encode 4-level priority encoders, daisy-chain arbiters, and grant-acknowledge state machines with predictable 25 ns latency, eliminating race conditions common in discrete 74LS series glue. The part's synchronous preset/reset structure and global three-state control support multi-drop bus wiring without external pull-ups on every line. Its industrial temperature grade ('I') and ceramic DIP package make it suitable for factory-floor controllers and Mil-spec chassis where plastic CPLDs are not qualified. Many legacy VMEbus peripheral cards still specify the EP610 family in their original 1980s/1990s BOMs, and Rochester Electronics is the authorized continuing source for sustaining production.
Recommended
State Machine and Protocol Converter Controllers
Designing custom serial protocols, RS-232/RS-422 handshake sequencers, or industrial fieldbus converters (e.g., legacy Profibus, Interbus, or proprietary fieldbus links) often requires a finite state machine with deterministic timing - the EP610LI-25's AND-OR array and per-macrocell flip-flop are purpose-built for this. With 100 MHz pipelined fMAX and 25 ns tPD, the part handles bit-banged UART, HDLC, or SPI conversion at typical industrial baud rates (up to ~10 Mbaud synchronous) while leaving cycles for watchdog and timeout logic. The windowed ceramic DIP allows field-reprogramming during protocol updates without replacing the IC, an advantage over one-time-programmable PAL/GAL alternatives. Sustained production via Rochester Electronics keeps long-life industrial protocols on air for decades.
Recommended
Military / Aerospace Sustaining Engineering
Defense and aerospace platforms originally designed around Altera Classic EPLDs in the 1980s-1990s - radar signal processors, avionics bus interfaces, naval communication systems - still depend on the EP610LI-25 because Mil-spec qualification, ceramic packaging, and full traceability are non-negotiable. The windowed ceramic DIP package supports UV erasure for firmware updates during depot-level maintenance, while the industrial temperature grade (-40 to +85 C) covers most Mil-spec operating envelopes. Rochester Electronics holds the authorized continuing-manufacturing rights for these legacy Altera parts, providing full traceability documentation required by defense procurement. The EP610 family is also pin-compatible across speed grades, allowing logistics organizations to stock a single part number that can be substituted across variants as needed.
Recommended
Industrial PLC and Process Control Backplanes
Programmable Logic Controllers (PLCs) and process-control rackmount I/O systems use the EP610LI-25 for I/O expansion decoding, optocoupler drive sequencing, and inter-module handshaking on legacy backplanes. With 16 macrocells and 300 usable gates, a single EP610LI-25 can manage the address decode, chip-select, and interrupt structure for a full 8-slot I/O rack, replacing a basket of discrete 74LS logic. The 'L' low-power CMOS variant minimizes backplane heat dissipation across hundreds of densely packed cards, important for sealed IP65 enclosures. Industrial temperature grade ('I') handles factory-floor thermal swings from cold-start mornings to summer load peaks. Continued production via Rochester Electronics means process-control integrators can sustain installed bases without forced PLC migration.
Recommended
Test & Measurement Legacy Instrument Repair
Classic bench-top instruments from HP/Agilent/Keysight, Tektronix, Fluke, and similar vendors built in the 1980s-1990s often contain Altera Classic EPLDs like the EP610LI-25 for front-panel decoding, display multiplexing, and GPIB/HPIB handshake logic. When these instruments require repair after decades of service, the EP610LI-25 is the only authorized replacement because modern CPLDs cannot be retrofitted into the original through-hole DIP socket. Rochester Electronics maintains continuing manufacture specifically to support this sustaining-repair market for test-and-measurement laboratories, calibration houses, and metrology institutes. UV-erasability also allows repair technicians to reprogram replacement parts with the original instrument firmware before installation, avoiding the need to source rare pre-programmed parts.
Recommended
Recommended Products Summary
Engineering reference data for EP610LI-25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610LI-20 | EP610LI-15 | EP610ILI-25 | EP610DC-25 | EP610DC-30 | EP610DC-20 |
|---|---|---|---|---|---|---|---|
| Package | Ceramic DIP-24 (windowed) | Ceramic DIP-24 (windowed) - same | Ceramic DIP-24 (windowed) - same | Ceramic DIP-24 (windowed) - same | Ceramic DIP-24 (windowed) - same | Ceramic DIP-24 (windowed) - same | Ceramic DIP-24 (windowed) - same |
| Brand | Rochester Electronics (Altera) | Rochester Electronics (Altera) | Rochester Electronics (Altera) | Rochester Electronics (Altera) | Rochester Electronics (Altera) | Rochester Electronics (Altera) | Rochester Electronics (Altera) |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 | 300 |
| Maximum tPD | 25 ns | 20 ns (faster) | 15 ns (faster) | 25 ns (same) | 25 ns (same) | 30 ns (slower) | 20 ns (faster) |
| Pipelined fMAX | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Power Variant | L (low-power CMOS) | L (low-power CMOS) | L (low-power CMOS) | L (low-power CMOS) | standard CMOS | standard CMOS | standard CMOS |
| Temperature Grade | I (industrial) | I (industrial) | I (industrial) | I (industrial) | C (commercial) | C (commercial) | C (commercial) |
Key Differentiators
- Authorized continuing-manufacturing source for the Altera EP610 family (vs Brokers / aftermarket EP610LI-25 stock)
- Same ceramic DIP-24 footprint as the entire EP610 speed-grade family (vs Modern plastic QFP CPLD alternatives)
- Industrial temperature grade (-40 to +85 C) in low-power CMOS 'L' variant (vs EP610DC-25 (commercial-grade, standard power))
Design Notes
Do not assume the EP610LI-25 is supported by modern Altera/Intel Quartus or Lattice Diamond toolchains - it requires the legacy Altera MAX+PLUS II or Classic compiler running on Windows XP/7 or DOS. Maintain a virtual machine with the original toolchain, a compatible parallel-port or USB-blaster programmer (e.g., ByteBlasterMV or LP6), and the EP610 JEDEC fuse-file output flow. Programming voltage and timing for the EP610 family differs from MAX II/MAX V CPLDs and following a modern CPLD programming guide will brick the part.
The EP610LI-25 windowed ceramic DIP package was designed for low-density legacy logic and has limited thermal headroom. Estimated: at 10 MHz with 16 I/O pins switching 50 pF loads, junction temperature rise is well under 5 C above ambient, so no heatsink is required. However, ensure the ceramic socket allows adequate airflow - sealed industrial enclosures should specify a socket with open top to permit UV erasure access during field updates.
Mount the EP610LI-25 in a low-profile UV-transparent socket (e.g., 24-pin machined-pin DIP socket with open top) to allow in-circuit UV erasure during field firmware updates. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of the VCC pin and a 10 uF tantalum bulk capacitor on the same supply rail. Keep TTL-level inputs and outputs separated by at least one trace-width from analog or high-impedance signal paths to avoid switching noise injection during state-machine transitions.
Compliance Information
Ceramic DIP legacy package compliance status not confirmed in verified web data - flag for procurement review. AEC-Q100 not applicable to EPLDs (automotive-grade logic not specified).
