EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
MPN: EP610PC-25T β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $52.96 | $52.96 |
| 10 | $47.5 | $475.00 |
| 100 | $39.8 | $3,980.00 |
| 500 | $33.2 | $16,600.00 |
| 1,000 | $28.95 | $28,950.00 |
EP610PC-25T Overview
A Classic EPLD is a one-time- or UV-programmable CMOS PLD positioned below the CPLD and FPGA tiers in the programmable-logic hierarchy. It sits architecturally between a PAL/GAL and a modern CPLD: more flexible than a fixed-AND/OR PAL, but simpler and lower-cost than a JTAG-configurable CPLD or SRAM-based FPGA. In a typical digital system the EP610 replaces multiple SSI/MSI 74LS/74HC glue-logic packages - address decoding, wait-state generation, interrupt steering - so designers reduce board area, BOM count, and assembly cost without writing HDL or purchasing a toolchain beyond a simple programmer.
Key features of the EP610PC-25T include: 25 ns tPD (pin-to-pin delay, commercial speed grade), 16 macrocells each with a configurable flip-flop, product-term allocation for both combinatorial and registered logic, 5 V Β±5% VCC operation, and an industry-standard JEDEC DIP-24 footprint compatible with UV-windowed EP610DC-25 ceramic parts on the same PCB. The T suffix denotes a tube-packaged shipping form, while the EP610PC-25 is shipped in tray; both share identical die and pinout.
Architecturally the EP610 uses Altera's Classic macrocell with sum-of-products logic feeding a programmable output cell that can be configured as registered, combinatorial, or bi-directional I/O. The device is programmed via an industry-standard 4-pin JTAG-style interface in production programming. Its CMOS EPROM-style non-volatile configuration means no boot PROM is required, simplifying board design. Designers should be aware that the device is NOT in-system programmable and must be erased by UV light if a windowed CERDIP variant is used, or discarded if a plastic one-time-programmable (OTP) variant like the EP610PC-25T is used.
Typical applications include industrial control boards, telecom line cards, legacy peripheral adapters, address decoding for microprocessors, and replacement of 74LS-series glue logic. The EP610PC-25T is also widely used for long-life-cycle embedded systems where supply continuity for over a decade is required.
When designing with the EP610PC-25T, plan for a 5 V supply rail, place a 0.1 Β΅F decoupling capacitor adjacent to each VCC pin, and budget for the OTP programming step (the device cannot be reprogrammed in-circuit). Engineers migrating from EP610PC-25 should note identical pinout, identical die, and identical speed grade.
This page synthesizes distributor pricing, drop-in alternatives drawn from the Altera Classic device family, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP610PC-25T β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PC-25T (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Technology, Family, Propagation Delay (tPD).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610PC-25
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEP610IPC-25
β Drop-Inβ In Stock
$8.85 / Unit
View Datasheet βEP610LI-25
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$17.25 / Unit
View Datasheet βEP610DC-25
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP610PC-20T
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEP610PC-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$17.5 / Unit
View Datasheet βEP610PC-25T Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel (formerly Altera) |
| Distributor / Stocking Source | Rochester Electronics, LLC |
| Device Family | Altera Classic EPLD - EP610 |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) |
| Logic Capacity | 300 usable gates |
| Macro Cells | 16 |
| Registers | 16 |
| User I/Os | 16 |
| Propagation Delay (tPD) | 25 ns (speed grade 25) |
| Pipelined Data Rate | up to 100 MHz |
| Supply Voltage (VCC) | 5 V |
| Process Technology | ECMOS (CMOS, EPROM-based) |
| Package | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) |
| Programming Method | OTP (one-time programmable) via Altera programming hardware |
| Mounting Type | Through-hole |
| Shipping Form (T suffix) | Tube |
EP610PC-25T Pin Configuration
| Pin 1 | I/O0 β User I/O pin 0 (bidirectional, programmable) |
| Pin 2 | I/O1 β User I/O pin 1 (bidirectional, programmable) |
| Pin 3 | I/O2 β User I/O pin 2 (bidirectional, programmable) |
| Pin 4 | I/O3 β User I/O pin 3 (bidirectional, programmable) |
| Pin 5 | I/O4 β User I/O pin 4 (bidirectional, programmable) |
| Pin 6 | I/O5 β User I/O pin 5 (bidirectional, programmable) |
| Pin 7 | I/O6 β User I/O pin 6 (bidirectional, programmable) |
| Pin 8 | I/O7 β User I/O pin 7 (bidirectional, programmable) |
| Pin 9 | I/O8 β User I/O pin 8 (bidirectional, programmable) |
| Pin 10 | GND β Ground (0 V) |
| Pin 11 | I/O9 β User I/O pin 9 (bidirectional, programmable) |
| Pin 12 | I/O10 β User I/O pin 10 (bidirectional, programmable) |
| Pin 13 | I/O11 β User I/O pin 11 (bidirectional, programmable) |
| Pin 14 | I/O12 β User I/O pin 12 (bidirectional, programmable) |
| Pin 15 | I/O13 β User I/O pin 13 (bidirectional, programmable) |
| Pin 16 | I/O14 β User I/O pin 14 (bidirectional, programmable) |
| Pin 17 | I/O15 β User I/O pin 15 (bidirectional, programmable) |
| Pin 18 | NC β Not connected (per datasheet) |
| Pin 19 | NC β Not connected (per datasheet) |
| Pin 20 | VCC β +5 V supply voltage |
| Pin 21 | NC β Not connected (per datasheet) |
| Pin 22 | NC β Not connected (per datasheet) |
| Pin 23 | NC β Not connected (per datasheet) |
| Pin 24 | NC β Not connected (per datasheet) |
Typical Applications
EP610PC-25T is suitable for 6 applications: Microprocessor Address Decoding, 74LS/74HC Glue-Logic Consolidation, Industrial Control State Machines, Legacy Telecom Line Cards, Test and Measurement Front-Ends, Aerospace and Defense Avionics (Legacy).
Microprocessor Address Decoding
The EP610PC-25T is a natural fit for 8-bit and 16-bit microprocessor address decoding, where a single 5 V device replaces 3-5 SSI/MSI 74LS138 or 74HC138 packages. Its 16 macrocells are sufficient to decode a full 16-bit address bus into 8-12 chip-select outputs, while 25 ns tPD keeps the propagation well inside one clock cycle at 8 MHz 8086 or 10 MHz 68000 bus speeds. The PDIP-24 footprint plugs directly into through-hole prototyping boards used in industrial controllers. Compared to a discrete 74LS138 decoder, the EP610PC-25T delivers more channels of decode in one package and lets the designer modify decode maps without board rework.
Recommended
74LS/74HC Glue-Logic Consolidation
Designers use the EP610PC-25T to consolidate scattered 74LS00, 74LS04, 74LS74, 74LS138, 74LS244, and 74LS373 glue-logic packages into a single OTP device. The 300-gate capacity and 16 macrocells can replace 4-8 small-scale packages, lowering BOM cost, assembly time, and board area. Pipelined data rates up to 100 MHz at 5 V VCC mean timing closure is straightforward when replacing HC-logic. The OTP plastic package makes the EP610PC-25T attractive for mature products where the design is locked and a high-volume single-chip drop-in is preferred over re-engineering with a CPLD.
Recommended
Industrial Control State Machines
The EP610PC-25T is widely deployed in long-life industrial controllers, PLC I/O boards, and motor-control cards where its 25 ns tPD, 16 macrocells, and 5 V operation match the timing envelope of 80C196, 8051, and PIC microcontroller peripherals. Each macrocell can hold a state register, enabling Mealy and Moore state machines that run tens of kHz without external logic. The 0-70 Β°C commercial temperature range covers most factory-floor enclosures. Rochester Electronics' ongoing-lifecycle manufacturing guarantees continuity of supply for 10-15 year industrial programs.
Recommended
Legacy Telecom Line Cards
Telecom line-interface cards designed in the 1990s still ship with the EP610PC-25T for alarm encoding, timeslot switching, and HDLC-channel grooming. Its 16 user I/Os at 100 MHz pipelined data rate handle T1/E1 framers and DS0 channel banks without timing slips. The 5 V VCC rail matches the legacy -48 V isolated backplane supply rails found in central-office equipment. The OTP plastic package is preferred in this application because field re-programmability is undesirable for telecom-certified hardware.
Recommended
Test and Measurement Front-Ends
Benchtop instruments such as logic analyzers, protocol testers, and frequency counters use the EP610PC-25T for trigger sequencing, channel multiplexing, and BCD-to-binary conversion front-ends. The 25 ns tPD aligns well with 40 MHz acquisition logic, and 16 macrocells can implement multi-stage trigger sequencers that previously required discrete 74LS-series logic. The PDIP-24 package is socket-friendly, allowing field replacement on legacy test gear. The non-volatile OTP behavior ensures the trigger personality is preserved across power cycles without boot time.
Recommended
Aerospace and Defense Avionics (Legacy)
The EP610PC-25T and its industrial-temperature sibling EP610IPC-25 are qualified for use in older avionics LRUs (line-replaceable units) and ground-support equipment where the design has been certified to DO-254 / MIL-STD-883 and cannot be modified. The 5 V supply, proven CMOS process, and OTP plastic DIP package align with avionics box-build standards from the late 1980s and 1990s. For new programs, designers migrate to radiation-tolerant FPGAs, but the EP610PC-25T continues to be sourced for legacy LRU sustainment under the Defense Logistics Agency's ongoing-lifecycle contracts.
Recommended
Recommended Products Summary
Engineering reference data for EP610PC-25T β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-25 | EP610IPC-25 | EP610DC-25 | EP610PC-20T | EP610LI-25 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PDIP-24 | PDIP-24 - same | PDIP-24 - same | CERDIP-24 - same pin count, ceramic | PDIP-24 - same | LCC-28 - different |
| Propagation Delay (tPD) | 25 ns | 25 ns | 25 ns | 25 ns | 20 ns (faster) | 25 ns |
| Macro Cells | 16 | 16 | 16 | 16 | 16 | 16 |
| User I/Os | 16 | 16 | 16 | 16 | 16 | 16 |
| Supply Voltage (VCC) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Programmability | OTP (plastic) | OTP (plastic) | OTP (plastic) | Windowed UV-erasable | OTP (plastic) | OTP (ceramic) |
| Operating Temperature | 0 to +70 Β°C | 0 to +70 Β°C | -40 to +85 Β°C (industrial) | 0 to +70 Β°C | 0 to +70 Β°C | -40 to +85 Β°C (industrial) |
Key Differentiators
- Industry-proven Classic EPLD architecture with 25-year supply track record (vs EP610PC-20T)
- Plastic PDIP-24 OTP package for lowest BOM cost (vs EP610DC-25)
- Ongoing-lifecycle supply via Rochester Electronics (vs Modern CPLDs (MAX II, ispMACH))
Design Notes
Estimated: the EP610PC-25T draws approximately 100-150 mA quiescent current at 5 V VCC during normal operation, peaking higher during programming. Designers should budget a 5 V regulator with at least 250 mA headroom and place a 0.1 Β΅F decoupling capacitor adjacent to the VCC pin (pin 20) plus a 10 Β΅F bulk capacitor on the 5 V rail within 1 inch of the device. The CMOS design draws negligible current on un-driven I/O pins, so input pins should not be left floating - tie them to VCC or GND through 10 kΞ© resistors to avoid I_CC drift during transitions.
The EP610PC-25T plastic package is ONE-TIME PROGRAMMABLE (OTP). Once the JEDEC fuse pattern is blown, the device cannot be erased or re-programmed. Prototype boards should use the windowed CERDIP variant EP610DC-25 or the same-footprint industrial EP610IPC-25 until the design is fully validated, then migrate to EP610PC-25T for production. Programming requires legacy Altera programming hardware (e.g., LP6, PL-ASAP); no modern JTAG or USB programmer supports the Classic EPLD family. Verify fuse map with verification mode before blowing final fuses.
Estimated: at 5 V VCC and 100 MHz toggle frequency, internal power dissipation for the EP610PC-25T is approximately 0.5-0.75 W, well within the PDIP-24 package's thermal envelope (ΞΈ_JA β 70 Β°C/W). At 25 Β°C ambient, junction temperature stays below 80 Β°C, so no heatsink is required. However, designers mounting the device in an enclosed industrial enclosure should derate ambient temperature by 10 Β°C above the nominal maximum because the plastic DIP package has limited convective cooling. For continuous operation above 70 Β°C ambient, migrate to the industrial-temperature variant EP610IPC-25 or EP610LI-25.
Compliance Information
Compliance status was not published in the verified web data or Rochester Electronics product page snippet for EP610PC-25T. Plastic PDIP-24 packages from this era typically contain lead-bearing solder finishes; engineers should verify with Rochester's datasheet or compliance letter before Pb-free reflow assembly. AEC-Q100 is not applicable - this is an industrial/commercial legacy EPLD, not an automotive-qualified device. Conflict-mineral status is not stated in available data.
