EP610PC-15 vs EP610DC-10 Comparison
Detailed side-by-side comparison of EP610PC-15 by Altera and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-15 | EP610DC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.50 | $7.95 |
| Family | Classic EPLD | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Usable Gates | 300 gates | β |
| Macrocells | 16 | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | β |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | β |
| Technology | CMOS | CMOS, EPROM-based (UV-erasable) |
| Architecture | PAL-type, sum-of-products AND/OR array | β |
| TTL Emulation | 100% TTL compatible | β |
| Package | PDIP-24 (plastic DIP, 24-pin) | 24-pin CDIP (Ceramic DIP, windowed) |
| Pin Count | 24 pins | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified web data] |
| Development Tool | Altera MAX+PLUS II | β |
| Logic Test Circuitry | On-board for AC/DC verification | β |
| Device Family | β | Altera Classic EPLD |
| Maximum Pipelined Data Rate | β | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | β | 10 ns |
| Speed Grade | β | -10 |
| Supply Voltage | β | 5 V (single supply) |
| I/O Pins | β | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Logic Elements | β | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | β | UV-erasable EPROM |
| Reprogrammable | β | Yes (UV erase window on package) |