EP610PC-15 vs EP610JI-30 Comparison

Detailed side-by-side comparison of EP610PC-15 by Altera and EP610JI-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610PC-15 EP610JI-30
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $17.50 $9.40
Family Classic EPLD Altera Classic EPLD (EP610)
Device Type EPLD (Erasable Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Usable Gates 300 gates β€”
Macrocells 16 16
Logic Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) β€”
Maximum Counter Frequency 100 MHz (per family datasheet) β€”
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 5 V (single supply) β€”
Technology CMOS β€”
Architecture PAL-type, sum-of-products AND/OR array β€”
TTL Emulation 100% TTL compatible β€”
Package PDIP-24 (plastic DIP, 24-pin) CQCC28 (windowed ceramic JLCC, J-bend)
Pin Count 24 pins β€”
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C (industrial, per EP610 family suffix convention)
Mounting Type Through-Hole (DIP) Surface Mount (JLCC)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Development Tool Altera MAX+PLUS II β€”
Logic Test Circuitry On-board for AC/DC verification β€”
Propagation Delay (tpd) β€” 30 ns (max)
Product Terms β€” 160
Dedicated Inputs β€” 4
I/O Pins β€” 16
External Clocks β€” 2
Supply Voltage β€” 5 V (single supply)
Process Technology β€” CMOS
Package Code β€” JLCC-28 / CQCC28
Erasure Method β€” Ultraviolet (UV) via top window
Programming β€” Altera Logic Programmer compatible
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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