EP610PC-15 vs EP610PC-20 Comparison
Detailed side-by-side comparison of EP610PC-15 by Altera and EP610PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-15 | EP610PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.50 | $47.80 |
| Family | Classic EPLD | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Usable Gates | 300 gates | 300 |
| Macrocells | 16 | β |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | β |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V Β±10% |
| Technology | CMOS | β |
| Architecture | PAL-type, sum-of-products AND/OR array | β |
| TTL Emulation | 100% TTL compatible | β |
| Package | PDIP-24 (plastic DIP, 24-pin) | PDIP-24 |
| Pin Count | 24 pins | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Mounting Type | Through-Hole (DIP) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (legacy PDIP) |
| Development Tool | Altera MAX+PLUS II | β |
| Logic Test Circuitry | On-board for AC/DC verification | β |
| Logic Elements | β | 16 macrocells |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Operating Frequency | β | 100 MHz (pipelined) |
| Number of Pins | β | 24 |
| Process Technology | β | CMOS EPROM |
| Programmable Flip-Flops | β | 16 |
| Input Pins | β | 24 |
| Output Pins | β | 16 |
| I/O Compatibility | β | TTL |
| Program/Erase Method | β | UV (windowed) or OTP |